Prosecution Insights
Last updated: July 17, 2026
Application No. 18/845,879

WIRING BOARD AND METHOD FOR MANUFACTURING WIRING BOARD

Non-Final OA §103§112
Filed
Sep 11, 2024
Priority
Mar 16, 2022 — JP 2022-041769 +1 more
Examiner
TSO, STANLEY
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Aoi Electronics Co. Ltd.
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
382 granted / 502 resolved
+8.1% vs TC avg
Strong +33% interview lift
Without
With
+33.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
33 currently pending
Career history
532
Total Applications
across all art units

Statute-Specific Performance

§103
91.5%
+51.5% vs TC avg
§102
6.0%
-34.0% vs TC avg
§112
1.8%
-38.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 502 resolved cases

Office Action

§103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 19-22 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 6/11/2026. Applicant alleges that the cited references do not discloses certain limitations as set forth in independent claim 10, and therefore the claimed invention possesses special technical features to form an inventive concept. Therefore, Applicant alleges that the restriction requirement should be withdrawn. The Examiner respectfully disagrees because the claimed invention is not patentable in view of the cited prior art. See the rejections below. As such, Applicant’s traversal is not persuasive. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 14-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The terms “the via hole has a rough inner surface” in claim 14 and “the protrusion holes have rough inner surfaces” in claim 15 are relative terms which renders the claim indefinite. The term “rough” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. In order to expedite prosecution, the term “rough” is construed as how it might be interpreted by a person having ordinary skill in the art. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 10-11 and 13-18 are rejected under 35 U.S.C. 103 as being unpatentable over “Ito” (JP 2005244108) in view of “Park” (US 2017/0025384). Regarding claim 10, Ito discloses 10. A wiring board comprising: an external connection terminal of which bottom surface is visible (Figs. 1, 3, 7-8, [0020]-[0022], [0026], [0028], [0030]; the wiring board 1 comprising the terminal pad PD1 which is an external connection terminal of which bottom surface is visible); an insulating layer around the external connection terminal, the insulating layer consisting of a single layer (Figs. 1, 3, 7-8, [0020]-[0022], [0026], [0028], [0030]; the dielectric layer B1a is a single layer around the terminal pad PD1); and a wiring layer that is layered on the insulating layer and is electrically connected with the external connection terminal through a via provided in the insulating layer (Figs. 1, 3, 7-8, [0020]-[0022], [0026], [0028], [0030]; the conductor layer at the top of the dielectric layer B1a is electrically connected to the terminal pad PD1 through the via conductor VA); wherein the bottom surface of the external connection terminal and a bottom surface of the insulating layer are in a same plane (Figs. 1, 3, 7-8, [0020]-[0022], [0026], [0028], [0030]; the bottom surface of the terminal pad PD1 and a bottom surface of the dielectric layer B1a are in a same plane), and the external connection terminal has a bottom conductive layer that constitutes the bottom surface of the external connection terminal (Figs. 1, 3, 7-8, [0020]-[0022], [0026], [0028], [0030]; the terminal pad PD1 has a bottom conductive layer that constitutes the bottom surface of the terminal pad PD1), the external connection terminal including protrusions formed to protrude upward into the insulating layer on a top surface of the bottom conductive layer (Figs. 1, 3, 7-8, [0020]-[0022], [0026], [0028], [0030]; the terminal pad PD1 has conductor portions 11a formed to protrude upward into the dielectric layer B1a on a top surface of the terminal pad PD1). Ito does not disclose the external connection terminal including a plurality of columnar protrusions. Park discloses the external connection terminal including a plurality of columnar protrusions (Figs. 1-2, 8C, [0073]; a plurality of columnar protruding portions 84). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Ito’s connection terminal with Park’s columnar protrusions in order to increase the stability and reliability of the through via connection structure, as suggested by Park at [0004]. Regarding claim 11, Ito in view of Park discloses the claimed invention as applied to claim 10, above. Ito does not disclose the limitations of claim 11. Park discloses 11. The wiring board according to claim 10, wherein the via has a larger diameter than the protrusions, and the plurality of protrusions are arranged to surround the via (Fig. 8C, [0042]; the via 30 has a larger diameter than the protrusions 84, and the plurality of protrusions 84 are arranged to surround the via 30). Regarding claim 13, Ito in view of Park discloses the claimed invention as applied to claim 10, above. Ito discloses 13. The wiring board according to claim 10, wherein the plurality of protrusions are arranged such that, when a distance from a center of the bottom conductive layer to an outer periphery of the bottom conductive layer is R, a distance between each protrusion and the outer periphery of the bottom conductive layer is equal to or smaller than R/3 (Figs. 1, 3, 7-8, [0020]-[0022], [0026], [0028], [0030]; the protrusions are arranged at the outer periphery of the bottom conductive layer, thus this distance is zero, which is smaller than R/3). Regarding claim 14, Ito in view of Park discloses the claimed invention as applied to claim 10, above. Ito discloses 14. The wiring board according to claim 10, wherein the via is formed in a via hole formed in the insulating layer and the via hole has a rough inner surface (Figs. 1, 3, 7-8, [0020]-[0022], [0026], [0028], [0030]; the via conductor VA has a via hole that has a rough inner surface. Examiner’s note: This limitation is construed as any degree of roughness. See the 112 rejection above.). Regarding claim 15, Ito in view of Park discloses the claimed invention as applied to claim 10, above. Ito discloses 15. The wiring board according to claim 10, wherein the protrusions are formed in protrusion holes formed in the insulating layer and the protrusion holes have rough inner surfaces (Figs. 1, 3, 7-8, [0020]-[0022], [0026], [0028], [0030]; the protrusions have holes that have a rough inner surface. Examiner’s note: This limitation is construed as any degree of roughness. See the 112 rejection above.). Regarding claim 16, Ito in view of Park discloses the claimed invention as applied to claim 10, above. Ito discloses 16. The wiring board according to claim 10, wherein the bottom conductive layer is electrically connected with the wiring layer through the protrusions (Figs. 1, 3, 7-8, [0020]-[0022], [0026], [0028], [0030]; the terminal pad PD1 is electrically connected with the wiring layer through the protrusions). Ito does not disclose the protrusions are formed in protrusion holes formed in the insulating layer. Park discloses the protrusions are formed in protrusion holes formed in the insulating layer (Fig. 8C, [0042]; the protrusions 84 , are formed in protrusion holes formed in the insulating layer). Regarding claim 17, Ito in view of Park discloses the claimed invention as applied to claim 10, above. Ito does not disclose the limitations of claim 17. Park discloses 17. The wiring board according to claim 10, wherein the protrusions are 3 to 32 columnar members (Fig. 8C, [0042]; the protrusions 84 are 3 to 32 columnar members). Regarding claim 18, Ito in view of Park discloses the claimed invention as applied to claim 10, above. Ito does not disclose the limitations of claim 17. Ito discloses 18. The wiring board according to claim 10, wherein the wiring layer is formed on a top surface of the insulating layer (Figs. 1, 3, 7-8, [0020]-[0022], [0026], [0028], [0030]; the conductor layer at the top of the dielectric layer B1a is formed on a top surface of the dielectric layer B1a). Ito does not disclose the plurality of protrusions are formed to have a thickness not reaching the wiring layer. Park discloses the plurality of protrusions are formed to have a thickness not reaching the wiring layer (Figs. 1-2, 8C, [0073]; a plurality of columnar protruding portions 84 are formed to have a thickness not reaching the wiring layer). Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Ito in view of Park and “Wakabayashi” (JPH10242332). Regarding claim 12, Ito in view of Park discloses the claimed invention as applied to claim 10, above. Ito does not disclose the limitations of claim 12. Park discloses 12. The wiring board according to claim 10, wherein the plurality of protrusions are arranged to surround the via (Fig. 8C, [0042]; Fig. 8C, [0042]; the plurality of protrusions 84 are arranged to surround the via 30). Wakabayashi discloses the via includes a plurality of columnar parts (Fig. 1, [0010]; the internal conductive portions 4a, 4b are a via that includes a plurality of columnar parts). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Ito’s connection terminal, as modified by Park, with Wakabayashi via that includes a plurality of columnar protrusions so that the bonding area between the connection pad and the internal conductive portion can be increased, as suggested by Wakabayashi at [0008]. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANLEY TSO whose telephone number is (571)270-0723. The examiner can normally be reached Tu-Thurs 6am-6pm, alt M 6am-2pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Thompson can be reached at 571-272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STANLEY TSO/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Sep 11, 2024
Application Filed
Sep 11, 2024
Response after Non-Final Action
Jun 24, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
99%
With Interview (+33.4%)
2y 3m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 502 resolved cases by this examiner. Grant probability derived from career allowance rate.

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