DETAILED ACTION
[1] Remarks
I. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Claims 1-10 are pending and have been examined, where claims 1-4 and 6-10 is/are rejected and claim 5 is objected. Explanations will be provided below.
III. Inventor and/or assignee search were performed and determined no double patenting rejection(s) is/are necessary.
IV. Patent eligibility (updated in 2019) shown by the following: Claims 1-10 pass patent eligibility test because there is/are no limitation or a combination of limitations amounting to an abstract idea. Also, the following limitation or the combinations of the limitations: “the image of the defect being obtained by imaging the defect that occurs on a surface of an object, and the feature extraction model being configured to extract, from an input image, an image feature that decreases a distance between similar images; circuitry configured to determine a representative point for each classification, based on one or more image features that are extracted from respective images of defects by using the feature extraction mode” effects a transformation or a reduction of a particular article to a different state or thing / adds a specific limitation(s) other than what is well-understood, routine and conventional in the field, or adding unconventional steps that confine the claim to a particular useful application and providing improvements to the technical field of wafer defect detection, which recite additional elements that integrate the judicial exception into a practical application and amounting significant more.
[2] Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
Use of the word “means” (or “step for”) in a claim with functional language creates a rebuttable presumption that the claim element is to be treated in accordance with 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph). The presumption that 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph) is invoked is rebutted when the function is recited with sufficient structure, material, or acts within the claim itself to entirely perform the recited function. Absence of the word “means” (or “step for”) in a claim creates a rebuttable presumption that the claim element is not to be treated in accordance with 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph). The presumption that 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph) is not invoked is rebutted when the claim element recites function but fails to recite sufficiently definite structure, material or acts to perform that function.
Claim elements in this application that use the word “means” (or “step for”) are presumed to invoke 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Similarly, claim elements that do not use the word “means” (or “step for”) are presumed not to invoke 35 U.S.C. 112(f) except as otherwise indicated in an Office action.
Claim(s) 1-8 are not interpreted under 35 U.S.C. 112(f) or pre-AIA U.S.C. 112 6th paragraph because of the following reason(s): limitations are modified by sufficient structure or material for performing the claimed function.
Claim(s) 9-10 do not require 35 U.S.C. 112(f) or pre-AIA U.S.C. 112 6th paragraph interpretation because they are method claims and / or they are CRM claims.
Upon examination of the specification and claims, the examiner has determined, under the best understanding of the scope of the claim(s), rejection(s) under 35 U.S.C. 112(a)/(b) is not necessitated because of the following reasons: sufficient support are provided in the written description / drawings of the invention.
[3] Grounds of Rejection
Claim Rejections - 35 USC § 103
1. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1-4, 6 and 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu (US 20190287230) in view of Iwanaga (US 20110007961).
Regarding claim 1, Lu discloses a defect analyzer comprising:
a memory that stores feature extraction model that is trained based on learned data in which information indicating a classification of each defect is added to an image of the defect (see paragraph 22, The non-transitory computer-readable storage medium comprises one or more programs for executing a model on one or more computing devices, where the model is trained using semi-supervised machine learning based on only defect-free training images of semiconductor devices, where the model is configured to receive an image of a wafer and determine presence of one or more anomalies in the image),
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the image of the defect being obtained by imaging the defect that occurs on a surface of an object, and the feature extraction model being configured to extract, from an input image, an image feature that decreases a distance between similar images (see figure 2 illustration above, also see paragraph 20, a distance between the image and the defect-free training images in a feature space and determining, using the processor, if the image is an outlier based on the distance); and
circuitry configured to determine a representative point for each classification, based on one or more image features that are extracted from respective images of defects by using the feature extraction mode (see figure 1, determine presence of one or more anomalies in an image using model).
Lu is silent in disclosing output information indicating a relation between classifications, based on one or more distances that are each between representative points.
Iwanaga discloses output information indicating a relation between classifications, based on one or more distances that are each between representative points (see paragraph 104, This k-NN method is the method of comparing the feature amounts of the defect D inputted from the feature amount calculation unit 232 with the feature amount data of the defects D previously stored in the storage unit 220 on a feature amount space and outputting the classification class that the most analogous, nearest in distance, feature amount data, namely, the nearest-neighbor feature amount data belongs to).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include output information indicating a relation between classifications, based on one or more distances that are each between representative points
because to assess image structural relationships, and measure how distinct or overlapping different groups are in a feature space, which improves to similarity measures and avoid misclassifications.
Regarding claim 2, Lu discloses the defect analyzer according to claim 1, wherein the circuitry is configured to receive an input of a verification image that is obtained by imaging the surface of the object (see figure 2, defect on surface is read as the input image); generate, as a verification feature, the image feature that is extracted from the verification image by using the feature extraction model (see figure 2, the encoder is the feature extractor); and
Iwanaga discloses estimate a classification for the verification image based on a distance between the verification feature and each of the representative points (see paragraph 104, This k-NN method is the method of comparing the feature amounts of the defect D inputted from the feature amount calculation unit 232 with the feature amount data of the defects D previously stored in the storage unit 220 on a feature amount space and outputting the classification class that the most analogous, nearest in distance, feature amount data, namely, the nearest-neighbor feature amount data belongs to). See the motivation for claim 1.
Regarding claim 3, Iwanaga discloses the defect analyzer according to claim 2, wherein the circuitry is configured to extract, from the learned data, the image of the defect that is similar to the verification image, based on one or more distances that are each between image features (see paragraph 104, this k-NN method is the method of comparing the feature amounts of the defect D inputted from the feature amount calculation unit 232 with the feature amount data of the defects D previously stored in the storage unit 220 on a feature amount space and outputting the classification class that the most analogous, nearest in distance, feature amount data, namely, the nearest-neighbor feature amount data belongs to). See the motivation for claim 1. Also employing verification images improves defect detection in wafer, semiconductor manufacturing process.
Regarding claim 4, Iwanaga discloses the defect analyzer according to claim 1, wherein the circuitry is configured to determine a consolidated classification that includes given classifications for which a distance between representative points is decreased (see paragraph 105, Upper k pieces of the sorted distance data are extracted, where a most frequent classification class is found in the frequency distribution of the extracted data, where the k upper pieces of sorted in decreasing order and is consolidated into k nearest neighbors); extraction model based on the learned data to which information indicating the consolidated classification is assigned (see paragraph 105, classification method in the classification unit 233, the sum of squares of deviation (distance) of the feature amounts of the defect D from the feature amount calculation unit 232 and every piece of feature amount data in the storage unit 220 is calculated first, the calculated distance data are sorted in ascending order). See the motivation for claim 1. Also, employing K nearest neighbors are easy to implement, and requires no training period.
Regarding claim 6, Iwanaga discloses the defect analyzer according to claim 2, wherein the circuitry is configured to compare the distance between the verification feature and each of representative points, with a threshold, and estimate the classification for the verification image (see figure 10, where T difference image, paragraph 104, a more suitable classification class from a frequency distribution of classification classes that upper k pieces of the analogous feature amount data belong to is outputted, where the upper k piece belonging to the specific class, where k is read as the threshold). See the motivation for claim 1.
Regarding claims 9-10, see the rationale and rejection for claim 1.
3. Claims 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu (US 20190287230) in view of Iwanaga (US 20110007961) and Aspir (US 20020180468).
Regarding claim 7, the combination of Lu and Iwanaga as a whole discloses all the limitations of claim 6, but is silent in disclosing the defect analyzer according to claim 6, wherein upon occurrence of a condition in which there are given classifications for which the distance is less than or equal to the threshold, the circuitry is configured to estimate that the verification image matches the given classifications.
Aspir discloses the defect analyzer according to claim 6, wherein upon occurrence of a condition in which there are given classifications for which the distance is less than or equal to the threshold, the circuitry is configured to estimate that the verification image matches the given classifications (see paragraph 100, if the distance between neighboring features is less than the threshold, then the feature is classified as non-isolated).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include to estimate that the verification image matches the given classifications in order to measure how well an algorithm generalizes to new, unseen data and
It helps identify specific scenarios where a model fails, allowing developers to improve the system.
Regarding claim 8, Aspir discloses the defect analyzer according to claim 6, wherein upon occurrence of a condition in which there are no classifications for which the distance is less than or equal to the threshold, the circuitry is configured to estimate that the verification image matches a new classification different from the classifications (see paragraph 100, features that are classified as not isolated may be assigned an appropriate non-isolated classifier marker, or no classifier marker indicating its classification by default. It is appreciated that non-binary encoding, or other suitable markings, may be used to specify classification when a number of classifications, greater than two, is used to classify features). See the motivation for claim 7.
[4] Claim Objections
Claim(s) 5 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With regards to claim 5, the examiner cannot find any applicable prior art providing teachings for the following limitation(s): “the defect analyzer according to claim 1, wherein the information indicating the relation includes a heat map in which distances between representative points are each color-coded according to a length of the distance, a scatter plot in which the representative points are arranged based on multi- dimensional scaling, or a dendrogram in which the representative points are hierarchized based on hierarchical clustering”; in combination with the rest of the limitations of claim 1.
Pathangi (US 20200161081) discloses the defect analyzer according to claim 1, wherein the information indicating the relation includes a heat map in which distances between representative points are each color-coded according to a length of the distance (see figure 5 heat map), but is silent in disclosing a scatter plot in which the representative points are arranged based on multi- dimensional scaling, or a dendrogram in which the representative points are hierarchized based on hierarchical clustering.
CONTACT INFORMATION
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEX LIEW (duty station is located in New York City) whose telephone number is (571)272-8623 (FAX 571-273-8623), cell (917)763-1192 or email alexa.liew@uspto.gov. Please note the examiner cannot reply through email unless an internet communication authorization is provided by the applicant. The examiner can be reached anytime.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MISTRY ONEAL R, can be reached on (313)446-4912. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEX KOK S LIEW/Primary Examiner, Art Unit 2674 Telephone: 571-272-8623
Date: 5/30/26
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