Prosecution Insights
Last updated: August 06, 2026
Application No. 18/848,442

DATA SELECTION APPARATUS FOR SRAM ARRAY, STORAGE SYSTEM, AND SYSTEM ON CHIP

Final Rejection §103
Filed
Sep 18, 2024
Priority
Sep 01, 2023 — CN 202311118068.5 +1 more
Examiner
HUANG, MIN
Art Unit
2827
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Shenzhen Microbt Electronics Technology Co. Ltd.
OA Round
2 (Final)
90%
Grant Probability
Favorable
3-4
OA Rounds
1m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
759 granted / 840 resolved
+22.4% vs TC avg
Moderate +10% lift
Without
With
+9.7%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
17 currently pending
Career history
850
Total Applications
across all art units

Statute-Specific Performance

§101
3.5%
-36.5% vs TC avg
§103
54.9%
+14.9% vs TC avg
§102
23.4%
-16.6% vs TC avg
§112
8.4%
-31.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 840 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments filed 7/2/2026 have been fully considered but they are not persuasive. Applicant argues the amended claim 1 comprises “the plurality of D flip-flops are arranged in parallel at same positions between MUXs at adjacent stages; or, the D flip-flop array comprises a first portion and a second portion, wherein the first portion is arranged in parallel at same positions between MUXs at adjacent stages; and the second portion is arranged in parallel at different positions in the MUX array”, and is patentable: In prior art Ogata, Fig 10 reproduced below: FF 7311 and 7321 are matched to “first portion”, with parallel at same position between 702 and 7313/7323 MUXs, and FF 7312/7322 as “second portion” are parallel between the MUXs placed at different positions than that of FF of the “first portion”. PNG media_image1.png 392 580 media_image1.png Greyscale Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 4-6, 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ogata et al. (Patent 9684332), hereinafter as Ogata. Regarding claim 1, Ogata teaches a data selection apparatus for a static random-access memory (SRAM) array, comprising: a multiplexer (MUX) array, comprising a plurality of MUXs (Fig 10, 702 and 7313/7323 and 702); and a D flip-flop array (Fig 10, 7311/7312/7321/7322), comprising a plurality of D flip-flops, wherein the D flip-flop array is arranged inside the MUX array (Fig 10); an input of the MUX array is connected to an output of the SRAM array (the examiner is taking note that it is well known in the field that an IO circuit with mux circuit takes input from a SRAM array, e.g. Fig. 1 of Bhasin et al. (PGPUB 20200219579)); an output of the MUX array is connected to a bus; the MUX array is configured to select an output channel for outputting storage data in the SRAM array; and a D flip-flop being arranged on an output channel, is configured to truncate a timing path of the output channel; wherein the plurality of MUXs are multi-stage MUXs; the plurality of D flip-flops are arranged in parallel at same positions between MUXs at adjacent stages; or, the D flip-flop array comprises a first portion and a second portion, wherein the first portion is arranged in parallel at same positions between MUXs at adjacent stages; and the second portion is arranged in parallel at different positions in the MUX array. . Regarding claim 4, Ogata teaches a multiplexer with D flip-flop as in rejection of claim 1, except the details on delayed timing parameters between parts of the multiplexer. Claim 4 recites "a first timing delay", "a predefined timing delay threshold" and "a predefined difference threshold" without any further defining of a particular range; it has been ruled that it would have been obvious to one of ordinary skill in the art at the time the invention was filed to arrange a delay timing in specific range, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering an optimum or working ranges involves only routine skills in the art. In re Aller, 105 USPQ 233. Regarding claim 5, argument used in rejection of claim 4 applies. Regarding claim 6, Ogata teaches a storage system, comprising: a static random-access memory (SRAM) array, comprising a plurality of SRAM banks, each SRAM bank comprising a plurality of SRAMs (col 1, line 22); a multiplexer (MUX) array, comprising a plurality of MUXs (Fig 10); and a D flip-flop array (Fig 10), comprising a plurality of D flip-flops, wherein the D flip-flop array is arranged inside the MUX array; an input of each MUX is connected to an output of a SRAM bank corresponding to the respective MUX (argument used in rejection of claim 1 applies); an output of the MUX array is connected to a bus (Fig 10); the MUX array is configured to select an output channel for outputting storage data in the SRAM array (argument used in rejection of claim 1 applies); and a D flip-flop being arranged on an output channel, is configured to truncate a timing path of the output channel (Fig 10, D ff for adjusting timing). Regarding claim 9/10, argument used in rejection of claim 4 applies. Regarding claim 11, the examiner takes note that it is well known in the field that a SOC comprises a SRAM array. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MIN HUANG/Primary Examiner, Art Unit 2827
Read full office action

Prosecution Timeline

Sep 18, 2024
Application Filed
Apr 10, 2026
Non-Final Rejection mailed — §103
Jul 02, 2026
Response Filed
Jul 24, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12700468
MAGNETIC MEMORY
1y 10m to grant Granted Aug 04, 2026
Patent 12694933
MEMORY DEVICES, AND OPERATION METHOD THEREOF, MEMORY SYSTEMS
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Patent 12694910
MEMORY DEVICE AND OPERATION METHOD FOR DATA MOVEMENT WITHIN MEMORY SECTIONS AND THROUGH EXTERNAL INTERFACES OF MEMORY DEVICE
1y 11m to grant Granted Jul 28, 2026
Patent 12682972
CLOCK GENERATION CIRCUITS FOR MEMORY DEVICES WITH BUILT-IN SELF TEST
3y 0m to grant Granted Jul 14, 2026
Patent 12676174
METHOD AND DEVICE FOR SETTING IO PARAMETERS FOR COMMUNICATION BETWEEN SYSTEM ON CHIP AND MEMORY
1y 9m to grant Granted Jul 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
90%
Grant Probability
99%
With Interview (+9.7%)
2y 0m (~1m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 840 resolved cases by this examiner. Grant probability derived from career allowance rate.

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