DETAILED ACTION
This Office Action is responsive to the Applicant’s communication filed 31 August 2026. In view of this communication, claims 1-6 and 8-10 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Arguments
Applicant’s arguments, see page 5 of the Remarks, filed 31 August 2026, with respect to the rejection(s) of claim(s) 1, 2, and 6-8 under 35 USC §102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Matsuyama.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-2, 6, and 8 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Matsuyama et al. (US 2021/0170732 A1), hereinafter referred to as Matsuyama et al.
Regarding claim 1, Matsuyama et al. teaches a printed wiring board substrate comprising:
an insulating layer (10) (Figs. 1-2 and paragraph 32: insulating film 10);
a first copper foil (12) (Fig. 2 and paragraph 55: metal foil 12); and
a second copper foil (11) (Fig. 2 and paragraph 55: metal foil 11),
wherein the insulating layer (10) has a first main surface and a second main surface opposite to the first main surface (paragraph 55: multilayer film 10 has two main surfaces),
the insulating layer (10) includes a plurality of polyimide layers (2, 4) and a plurality of fluororesin layers (1, 3, 5) (paragraph 32: the multilayer film 10 comprises fluororesin layers 1, 3, and 5 and polyimide layers 2 and 4),
the total number of the plurality of polyimide layers (2, 4) and the plurality of fluororesin layers (1, 3, 5) is 5 or more (paragraph 32: the multilayer film 10 comprises 5 resin layers),
each of the plurality of polyimide layers (2, 4) and each of the plurality of fluororesin layers (1, 3, 5) are alternately stacked along a thickness direction of the insulating layer (10) (Fig. 1 and paragraph 32: the polyimide layers 2, 4 are stacked between fluororesin layers 1, 3, and 5),
one of the plurality of fluororesin layers (1, 3, 5) constitutes a first outermost layer (5) which is an outermost layer (5) on the side of the first main surface (Fig. 1 and paragraph 32: fluororesin layer 5 is stacked last such that it is the uppermost layer of the multilayer 10),
another one of the plurality of fluororesin layers (1, 3, 5) constitutes a second outermost layer (1) which is an outermost layer (1) on the side of the second main surface (Fig. 1 and paragraph 32: fluororesin layer 1 is stacked first such that it is the lowermost layer of the multilayer 10),
the first outermost layer (5) and the second outermost layer (1) each have a thickness of 1.0 µm or more and 50 µm or less (paragraph 39: the thickness of the fluororesin layers is 50µm or less),
a value obtained by dividing a total thickness of the plurality of polyimide layers (2, 4) by a thickness of the insulating layer (10) is 0.95 or less (paragraph 33: the total thickness of the fluororesin layers is 50% or more of the total thickness of the multilayer film, such that the total thickness of the polyimide layers if 50% or less of the thickness of the whole multilayer film), and
the first copper foil (12) and the second copper foil (11) are disposed on the first main surface and the second main surface, respectively (Fig. 2 and paragraph 55: the copper foils 11, 12 are arranged on the surfaces of multilayer film 10),
wherein the insulating layer (10) has a thickness of 130 µm or more and 170 µm or less (paragraph 51: the multilayer film is preferably 75 to 250 µm).
Regarding claim 2, Matsuyama et al. teaches the printed wiring board substrate according to claim 1, wherein the plurality of fluororesin layers are made of at least one material selected from the group consisting of tetrafluoroethylene-hexafluoropropylene copolymer, tetrafluoroethylene-perfluoroalkyl vinyl ether copolymer, and polytetrafluoroethylene (see paragraphs 34-36: the fluororesin may comprise polytetrafluoroethylene).
Regarding claim 6, Matsuyama et al. teaches the printed wiring board substrate according to claim 1, wherein the insulating layer (10) has a thermal expansion coefficient of 16.0 ppm/K or more and 100 ppm/K or less (see Table 1: the row “CTE (ppm/K)” shows that the thermal expansion coefficients of examples 1-7 are between 16.0 ppm/K and 100 ppm/K).
Regarding claim 8, Matsuyama et al. teaches a printed wiring board comprising:
an insulating layer (10) (Figs. 1-2 and paragraph 32: insulating film 10);
a first wiring (12) (Fig. 2 and paragraphs 5455 and 59: copper foil 12 which is laser etched to be used in a circuit); and
a second wiring (11) (Fig. 2 and paragraphs 5455 and 59: copper foil 11 which is laser etched to be used in a circuit),
wherein the insulating layer (10) has a first main surface and a second main surface opposite to the first main surface (paragraph 55: multilayer film 10 has two main surfaces),
the insulating layer (10) includes a plurality of polyimide layers (2, 4) and a plurality of fluororesin layers (1, 3, 5) (paragraph 32: the multilayer film 10 comprises fluororesin layers 1, 3, and 5 and polyimide layers 2 and 4),
the total number of the plurality of polyimide layers (2, 4) and the plurality of fluororesin layers (1, 3, 5) is 5 or more (paragraph 32: the multilayer film 10 comprises 5 resin layers),
each of the plurality of polyimide layers (2, 4) and each of the plurality of fluororesin layers (1, 3, 5) are alternately stacked along a thickness direction of the insulating layer (10) (Fig. 1 and paragraph 32: the polyimide layers 2, 4 are stacked between fluororesin layers 1, 3, and 5),
one of the plurality of fluororesin layers (1, 3, 5) constitutes a first outermost layer (5) which is an outermost layer (5) on the side of the first main surface (Fig. 1 and paragraph 32: fluororesin layer 5 is stacked last such that it is the uppermost layer of the multilayer 10),
another one of the plurality of fluororesin layers (1, 3, 5) constitutes a second outermost layer (1) which is an outermost layer (1) on the side of the second main surface (Fig. 1 and paragraph 32: fluororesin layer 1 is stacked first such that it is the lowermost layer of the multilayer 10),
the first outermost layer (5) and the second outermost layer (1) each have a thickness of 1.0 µm or more and 50 µm or less (paragraph 39: the thickness of the fluororesin layers is 50µm or less),
a value obtained by dividing a total thickness of the plurality of polyimide layers (2, 4) by a thickness of the insulating layer (10) is 0.95 or less (paragraph 33: the total thickness of the fluororesin layers is 50% or more of the total thickness of the multilayer film, such that the total thickness of the polyimide layers if 50% or less of the thickness of the whole multilayer film), and
the first wiring (12) and the second wiring (11) are disposed on the first main surface and the second main surface, respectively (Fig. 2 and paragraph 55: the copper foils 11, 12 are arranged on the surfaces of multilayer film 10),
wherein the insulating layer (10) has a thickness of 130 µm or more and 170 µm or less (paragraph 51: the multilayer film is preferably 75 to 250 µm).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsuyama et al. in view of Fukuchi (US 2017/0208680 A1), hereinafter referred to as Fukuchi.
Regarding claim 3, Matsuyama et al. teaches the printed wiring board substrate according to claim 1, but does not teach that the plurality of polyimide layers are made of polyimide having a relative dielectric constant of 2 or more and 4 or less.
Fukuchi does teach a polyimide resin having a relative dielectric constant of 2 or more and 4 or less (Fukuchi Table 2, row labeled “Example 21” teaches that the polyimide substrate has a dielectric constant of 3.2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the plurality of polyimide layers of Matsuyama et al. from a polyimide having a relative dielectric constant of 2 or more and 4 or less as taught by Fukuchi because Fukuchi teaches that polyimide resin is suitable for high frequency applications due to its low dielectric constant, low dissipation factor, and others (see Fukuchi paragraph 126). Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416."
Regarding claim 4, Matsuyama et al. teaches the printed wiring board substrate according to claim 1, but does not teach that the first copper foil and the second copper foil are made of electrolytic copper foil.
Fukuchi does teach that the first copper foil and the second copper foil may be made of electrolytic copper foil (Fukuchi paragraph 73: the copper foil plating may be an electrolytic copper foil).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the copper foil of Matsuyama et al. from an electrolytic copper foil as taught by Fukuchi because the electrolytic copper foil of Fukuchi improves circuit formability and reduces transmission loss by allowing the crystal grain size to be controlled (Fukuchi Abstract and paragraph 73). Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416."
Regarding claim 5, Matsuyama et al. teaches the printed wiring board substrate according to claim 1, but does not teach that the first copper foil and the second copper foil are made of rolled copper foil.
Fukuchi does teach that the first copper foil and the second copper foil may be made of rolled copper foil (Fukuchi paragraph 73: the copper foil may be a rolled copper foil).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the copper foil of Matsuyama et al. from a rolled copper foil as taught by Fukuchi because the rolled copper foil of Fukuchi improves circuit formability and reduces transmission loss by allowing the crystal grain size to be controlled (Fukuchi Abstract and paragraph 73). Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416."
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsuyama et al. in view of Kurihara et al. (US 2024/0328779 A1), hereinafter referred to as Kurihara et al.
Regarding claim 9, Matsuyama et al. teaches the printed wiring board according to claim 8, but does not teach that a transmission loss per 100mm of the first wiring at 50GHz and a transmission loss per 100mm of the second wiring at 50GHz are 7dB or less.
Kurihara et al. does teach that a transmission loss per 100mm of the first wiring at 50GHz and a transmission loss per 100mm of the second wiring at 50GHz are 7dB or less (Kurihara et al. paragraph 104 and Table 2: the copper foils’ transmission losses were measured at 50GHz and were consistently lower than 7dB).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the board of Matsuyama et al. with the low-loss copper foil of Kurihara because the reduction in loss improves signal transmission. Further, Kurihara teaches (paragraphs 84-86) a method for selecting a copper foil that has certain desirable high frequency characteristics. Therefore, it would have been routine optimization for one of ordinary skill in the art to select a copper foil with a transmission loss below 7dB/100mm. See In re Stepan, 868 F.3d 1342, 1346, 123 USPQ2d 1838, 1841 (Fed. Cir. 2017).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Luo-Larson (US 2017/0332479 A1), hereinafter referred to as Luo-Lawson, in view of Matsuyama et al.
Regarding claim 10, Luo-Lawson teaches a multilayer printed wiring board (100) comprising: a plurality of printed wiring boards (306, 308) (see Luo-Lawson Fig. 3 and paragraph 34: board 100 comprises multiple multilayered CCL boards 306, 308), but does not teach that each of the plurality of the printed wiring boards is the printed wiring board according to claim 8.
Matsuyama et al. does teach that each of the plurality of printed wiring boards may be the printed wiring board according to claim 8 (see above).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the multilayer printed wiring board of Luo-Lawson with the printed wiring boards of Matsuyama et al. because the printed wiring boards of Matsuyama et al. have improved dielectric and signal transmission properties (Matsuyama et al. paragraph 12).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John B Freal whose telephone number is (571)272-4056. The examiner can normally be reached Mon-Fri 7:00-3:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Thompson can be reached at (571)272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOHN B FREAL/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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