DETAILED ACTION
This Office Action is in response to the application filed on 20 September 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 14-19 objected to because of the following informalities: claims 14-19 recite in pertinent part “[t]he adhesive film for a semiconductor according to any one of claim…” (emphasis added). This appears to be a typographical error and for the purposes of examination, the phrase in question will be read as “[t]he adhesive film for a semiconductor according to claim….” Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4, 6-9, and 14-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hirano (US 2011/0006419 A1; hereinafter Hirano).
In regards to claim 1, Hirano teaches an adhesive film (2) for a semiconductor, comprising:
a thermosetting component ([0182]: heated and cured);
an elastomer [0111-0116]; and an inorganic filler [0030],
wherein the elastomer comprises an acrylic resin having a structural unit derived from a monomer having an aromatic ring [0125].
In regards to claim 2, Hirano teaches the limitations discussed above in addressing claim 1. Hirano further teaches the limitations wherein the adhesive film for a semiconductor has a thickness of 60 to 150 µm ([0130]: 10-75 µm).
In regards to claim 4, Hirano teaches the limitations discussed above in addressing claim 1. Hirano further teaches the limitations wherein the adhesive film for a semiconductor has a thickness of 25 to 80 µm ([0130]: 10-75 µm).
In regards to claim 6, Hirano teaches the limitations discussed above in addressing claim 1. Hirano further teaches the limitations wherein the elastomer further comprises an acrylic resin not having a structural unit derived from a monomer having an aromatic ring ([0116], [0186]: e.g. SG-708-6 or (meth)acrylic ester compound), and a weight average molecular weight of the acrylic resin not having a structural unit derived from a monomer having an aromatic ring is 500000 or more ([0116], [0186]: e.g. SG-708-6 or (meth)acrylic ester compound with weight average molecular weight of up to 1,000,000).
In regards to claim 7, Hirano teaches the limitations discussed above in addressing claim 1. Hirano further teaches the limitations wherein a content of the elastomer is 10 to 60% by mass, on the basis of a total amount of the adhesive film for a semiconductor ([0186]: e.g. 40%).
In regards to claim 8, Hirano teaches the limitations discussed above in addressing claim 1. Hirano further teaches the limitations wherein a content of the inorganic filler is 30 to 250 parts by mass, with respect to 100 parts by mass of the thermosetting component [0124].
In regards to claim 9, Hirano teaches the limitations discussed above in addressing claim 1. Hirano further teaches the limitations an integrated dicing/die bonding film, comprising: a dicing film ([0152]: (1)); and the adhesive film for a semiconductor according to claim 1, provided on the dicing film ([0152]: (2)).
In regards to claim 14, Hirano teaches the limitations discussed above in addressing claim 2. Hirano further teaches the limitations wherein the elastomer further comprises an acrylic resin not having a structural unit derived from a monomer having an aromatic ring ([0116], [0186]: e.g. SG-708-6 or (meth)acrylic ester compound), and a weight average molecular weight of the acrylic resin not having a structural unit derived from a monomer having an aromatic ring is 500000 or more ([0116], [0186]: e.g. SG-708-6 or (meth)acrylic ester compound with weight average molecular weight of up to 1,000,000).
In regards to claim 15, Hirano teaches the limitations discussed above in addressing claim 4. Hirano further teaches the limitations wherein the elastomer further comprises an acrylic resin not having a structural unit derived from a monomer having an aromatic ring ([0116], [0186]: e.g. SG-708-6 or (meth)acrylic ester compound), and a weight average molecular weight of the acrylic resin not having a structural unit derived from a monomer having an aromatic ring is 500000 or more ([0116], [0186]: e.g. SG-708-6 or (meth)acrylic ester compound with weight average molecular weight of up to 1,000,000).
In regards to claim 16, Hirano teaches the limitations discussed above in addressing claim 2. Hirano further teaches the limitations wherein a content of the elastomer is 10 to 60% by mass, on the basis of a total amount of the adhesive film for a semiconductor ([0186]: e.g. 40%).
In regards to claim 17, Hirano teaches the limitations discussed above in addressing claim 4. Hirano further teaches the limitations wherein a content of the elastomer is 10 to 60% by mass, on the basis of a total amount of the adhesive film for a semiconductor ([0186]: e.g. 40%).
In regards to claim 18, Hirano teaches the limitations discussed above in addressing claim 2. Hirano further teaches the limitations wherein a content of the inorganic filler is 30 to 250 parts by mass, with respect to 100 parts by mass of the thermosetting component [0124].
In regards to claim 19, Hirano teaches the limitations discussed above in addressing claim 4. Hirano further teaches the limitations wherein a content of the inorganic filler is 30 to 250 parts by mass, with respect to 100 parts by mass of the thermosetting component [0124].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10-13, 20, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hirano as applied to claims 1, 2, and 4 above, in view of Hashimoto et al. (WO 2020/157805 A1; citations to the attached machine translation; hereinafter Hashimoto).
In regards to claim 10, Hirano teaches the limitations discussed above in addressing claim 1. Hirano further teaches the adhesive film for a semiconductor according to claim 1 ((2); [0030], [0111-0116], [0125], [0182]). Hirano appears to be silent as to, but does not preclude, the limitations of a method for producing a semiconductor device, comprising causing a second semiconductor chip to adhere to a substrate on which a first semiconductor chip is mounted by the adhesive film, wherein the first semiconductor chip is embedded by the adhesive film. Hashimoto teaches the limitations of a method for producing a semiconductor device (200), comprising causing a second semiconductor chip (Waa) to adhere to a substrate (90(14)) on which a first semiconductor chip (Wa) is mounted by the adhesive film, wherein the first semiconductor chip is embedded by the adhesive film (10) (fig. 4). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Hirano with the aforementioned limitations taught by Hashimoto to have an adhesive that has a good embedding properties (Hashimoto “Industrial Applicability”).
In regards to claim 11, Hirano teaches the limitations discussed above in addressing claim 1. Hirano further teaches the adhesive film for a semiconductor according to claim 1 ((2); [0030], [0111-0116], [0125], [0182]). Hirano appears to be silent as to, but does not preclude, the limitations of a method for producing a semiconductor device, comprising causing a second semiconductor chip to adhere to a first semiconductor chip by the adhesive film, wherein a wire is connected to the first semiconductor chip, and a part or all of the wire is embedded by the adhesive film. Hashimoto teaches the limitations of a method for producing a semiconductor device (200), comprising causing a second semiconductor chip (Waa) to adhere to a first semiconductor chip (Wa) by the adhesive film (10), wherein a wire (88) is connected to the first semiconductor chip, and a part or all of the wire is embedded by the adhesive film (fig. 4). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Hirano with the aforementioned limitations taught by Hashimoto to have an adhesive that has a good embedding properties (Hashimoto “Industrial Applicability”).
In regards to claim 12, the combination of Hirano and Hashimoto teaches the limitations discussed above in addressing claim 10. Hashimoto further teaches the limitations wherein the first semiconductor chip (Wa) is a controller chip (pg. 9/para. 2 of the translation). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Hirano with the aforementioned limitations taught by Hashimoto to have an adhesive that has a good embedding properties (Hashimoto “Industrial Applicability”).
In regards to claim 13, the combination of Hirano and Hashimoto teaches the limitations discussed above in addressing claim 11. Hashimoto further teaches the limitations wherein the first semiconductor chip (Wa) is a controller chip (pg. 9/para. 2 of the translation). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Hirano with the aforementioned limitations taught by Hashimoto to have an adhesive that has a good embedding properties (Hashimoto “Industrial Applicability”).
In regards to claim 20, Hirano teaches the limitations discussed above in addressing claim 2. Hirano appears to be silent as to, but does not preclude, the limitations of a method for producing a semiconductor device, comprising causing a second semiconductor chip to adhere to a substrate on which a first semiconductor chip is mounted by the adhesive film, wherein the first semiconductor chip is embedded by the adhesive film. Hashimoto teaches the limitations of a method for producing a semiconductor device (200), comprising causing a second semiconductor chip (Waa) to adhere to a substrate (90(14)) on which a first semiconductor chip (Wa) is mounted by the adhesive film, wherein the first semiconductor chip is embedded by the adhesive film (10) (fig. 4). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Hirano with the aforementioned limitations taught by Hashimoto to have an adhesive that has a good embedding properties (Hashimoto “Industrial Applicability”).
In regards to claim 21, Hirano teaches the limitations discussed above in addressing claim 4. Hirano appears to be silent as to, but does not preclude, the limitations of a method for producing a semiconductor device, comprising causing a second semiconductor chip to adhere to a first semiconductor chip by the adhesive film, wherein a wire is connected to the first semiconductor chip, and a part or all of the wire is embedded by the adhesive film. Hashimoto teaches the limitations of a method for producing a semiconductor device (200), comprising causing a second semiconductor chip (Waa) to adhere to a first semiconductor chip (Wa) by the adhesive film (10), wherein a wire (88) is connected to the first semiconductor chip, and a part or all of the wire is embedded by the adhesive film (fig. 4). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Hirano with the aforementioned limitations taught by Hashimoto to have an adhesive that has a good embedding properties (Hashimoto “Industrial Applicability”).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALVIN Y CHOI whose telephone number is (571)270-7882. The examiner can normally be reached M-F 8-4 (Pacific Time).
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CALVIN CHOI
Patent Examiner
Art Unit 2812
/CALVIN Y CHOI/Primary Patent Examiner, Art Unit 2812
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