DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s election with traverse of Group I, claims 1-3 in the reply filed on 1/29/2026 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yudoovsky et al. (US2006/0254715A1).
Yudoovsky et al. teach cleaning semiconductor wafers in a cleaning line (i.e. the direction of cleaning modules 164a, 164B, and 164c in alignment) , which comprises at least 2 cleaning modules (164a, 164b, 164c, Fig.1, paragraph 35), and at least one gripping system, comprising 2 adjacent manipulators (168, 170), each configured to move over at least one of the cleaning modules, the method comprising in the cleaning modules, successfully treating a vertically oriented semiconductor during cleaning steps with a liquid of a respective cleaning step (paragraph 36), moving a first manipulator 168 through a first cleaning module (164A, paragraph 37), while the second manipulator 170 is between two cleaning modules 164B and 162.
Re claims 1 and 3, Yudoovsky et al. fail to teach a) the second manipulator between the slot in the cover of the first cleaning module and a slot in a cover of the second cleaning module and b) the second manipulator is arranged above the cover of the first cleaning module but not above the slot in the cover of the second cleaning module. It appears that the above limitations are directed to positioning of the first and second manipulators. Paragraph 38 teaches that the robots 168 and 170 are configured to move laterally along the rail 172 to facilitate access to the cleaning modules. Absent of a showing of criticality and/or unexpected results, it would have been obvious to a person of ordinary skill before the effective filing date of the claimed invention to position the robots at any desired location to facilitate access to the cleaning modules with the advantages of performing multiple processing steps on the substrate surface with greater efficiency and throughput. Re claim 2, refer to elements 164a, 164b, 164c of Fig. 1.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Jeong teaches a CMP process. Wada et al. teach a method of polishing a workpiece. Achkire et al. teach vertical transfer of the wafer. Miyazaki et al. teach a substrate processing apparatus. Maruyama et al. teach a substrate transfer band. Mockel et al. teach a cover for a cleaning module.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Sharidan Carrillo whose telephone number is (571)272-1297. The examiner can normally be reached M-F, 7:00am-4:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael Barr can be reached at 571-272-1414. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Sharidan Carrillo
Primary Examiner
Art Unit 1711
/Sharidan Carrillo/Primary Examiner, Art Unit 1711 bsc
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