DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yasuda (U.S PG Pub 20130089967A1) and Murakami (U.S Patent 4248750).
Regarding claims 1-2, Yasuda, drawn to the art of a temporary adhesive composition (Abstract) for use in the manufacture of thin wafers [0034], discloses an adhesive that has a component (A) which cures through a hydrosilylation reaction [0029]. Yasuda discloses the temporary adhesive being an adhesive for peelably ([0123-0124] & [0112-0113]) bonding between a support substrate and a circuit forming surface of a wafer for processing the back surface of the wafer [0109-0111]. Yasuda discloses as well the component (A) containing a polysiloxane (A1) wherein the polysiloxane includes an organopolysiloxane (a1) and an organopolysiloxane (a2) [0050 & 0075 & 0084], wherein both organopolysiloxanes have structures as claimed in instant claim 2 (see Synthesis Examples 2-2 and 3-2, as well as [0074-0076] for (a2) and [0050-0055] for (a1)). Further, Yasuda has disclosed a platinum group metal-based catalyst as part of the composition [0029 & 0075 & 0084-0085].
Yasuda has not explicitly disclosed a component (B) wherein the component B is a polyether-modified siloxane, however, this limitation is known from Murakami, as explained below.
Murakami, drawn also to the art of peelable films (Abstract), which can be used with glass (Column 1, lines 5-17 – Yasuda has also disclosed that the support substrate can be glass, see [0117] of Yasuda), discloses the temporary adhesive composition (Column 1, lines 45-56), containing a component (A) as is disclosed by Yasuda above (see Column 2, lines 28-45 & lines 48-50), and further a polyether-modified siloxane (Column 2, lines 40-42 & Column 4, lines 32-44 & Columns 4-5, lines 63-67 & 1-57 (depicting structures)). Murakami discloses that the addition of such a polyether modified siloxane reduces production of static during coating or after curing and provides an antistatic character whereby a uniform coat can be produced (Column 3, lines 30-38).
It would have been obvious to an ordinarily skilled artisan to have modified the adhesive of Yasuda, with the adhesive comprising a polyether-modified siloxane, as disclosed by Murakami, to arrive at the instant invention, in order to obtain an adhesive that has an antistatic character and where production of static during coating or after coating is reduced.
Regarding claims 3-4, Murakami has disclosed the polyether-modified siloxane having a structure as in B-1 (see Column 5, lines 6-33), wherein R is a polyoxyethylene or polyoxypropylene group (see Column 4, lines 32-43).
Regarding claim 5, Yasuda discloses the processing to be back-surface (i.e. non-circuit forming surface) polishing (i.e. grinding) of the wafer [0111].
Regarding claim 6, Yasuda discloses a first body (support substrate), a second body (wafer) and an adhesive layer in between formed of the adhesive of instant claim 1 [0110]. It is noted that the support substrate and wafer can be interchangeably interpreted as the first and second body, since the method of Yasuda is joining a support substrate and wafer with an adhesive layer and no other intervening layers in between or above.
Regarding claim 7, Yasuda has disclosed applying the adhesive onto a first body to form a coating film (Yasuda discloses the adhesive being applied to one or both of a support substrate and wafer – ‘at least one of the circuit forming surface and support substrate’) [0110], and performing a heating in a bonding state [0119] in which both the first and second body are in contact with the coating film (i.e. adhesive layer) [0118] so as to form a laminate with the first and second body bonded by the adhesive layer [0115-0119].
Regarding claims 8-9, as is noted already in the rejection of instant claim 6, the first and second body can be interchangeably interpreted as the support substrate or wafer, because the adhesive is applied to at least one of the circuit forming face of the wafer or the support substrate, and it will always be the case, regardless of the support substrate or wafer being interpreted as the first or second body, that the circuit forming surface will be facing a support substrate to bond the support substrate and wafer, such that a non-circuit forming (back surface) of the wafer is left open for processing (see [0115-0119]; [0110-0111]; [0121]).
Regarding claims 10-11 (nearly identical limitations with different dependencies), Yasuda discloses the steps of bonding the first and second body with the adhesive layer as claimed (see claim 7 rejection above as the language is identical for the bonding steps), and then discloses a step of delaminating i.e. peeling off the support substrate and wafer [0123-0125], after a processing step of grinding/polishing [0121] the back surface of the wafer (see generally [0110-0114]; [0115-0126]).
Regarding claims 12-15 (exact same limitations with the first body and second body being interchangeably a wafer and support substrate), as is noted above in the rejections of instant claims 6 and 8-9, either the support substrate or the wafer can be interchangeably interpreted as the first or second body, because it does not change the fact that the process applies an adhesive layer to a circuit forming surface of the wafer and then bonding the circuit forming surface of the wafer to a support substrate, wherein the back surface of the wafer is left open for processing. Interpreting the first body as a wafer or the second body as a substrate and vice-versa, does not change this process or the end result in any way, because the end result is always a circuit forming surface of the wafer being bonded to the support substrate by the adhesive layer.
Regarding claim 16, Yasuda has disclosed processing to be grinding i.e. polishing of the back surface of the wafer [0121 & 0111].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US-20070269659-A1, US-20080283415-A1, US-20140199533-A1, US-20210146697-A1 – all drawn to peelable and temporary adhesive layers and methods associated with them.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABHISHEK A PATWARDHAN whose telephone number is (571)272-8431. The examiner can normally be reached Monday to Friday 7:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael Orlando can be reached at (571)270-5038. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ABHISHEK A PATWARDHAN/Examiner, Art Unit 1746
/MICHAEL N ORLANDO/Supervisory Patent Examiner, Art Unit 1746