Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b), as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation " the N-channel field effect transistor" in “a drain of the P-channel field effect transistor is connected to a source of the N-channel field effect transistor” and “be connected to the source of the P-channel field effect transistor and the source of the N-channel field effect transistor”. There is insufficient antecedent basis for this limitation in the claim. For purposes of applying art examiner will select one of the two N-channel field effect transistors.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (Patent Application Publication 2023/0223089) in view of Miyaoka (U.S. Patent Application 5,265,060).
Claim 1. Lin discloses a storage array, comprising memory cells arranged in a matrix array (Lin Fig 7A), each memory cell comprising two memories (comprising R1 and R2), one field effect transistor (TC) and two N-channel field effect transistors alternately connected to the field effect transistor (TL and TR); wherein a source of the field effect transistor is connected to a drain of a N-channel field effect transistor (source of TC is connected to a drain of TL), a drain of the field effect transistor is connected to a source of the N-channel field effect transistor (drain of TC is connected to a source of TR), and the two memories are respectively configured to (configured to is functional language) be connected to the source of the field effect transistor (R2 is connected to source of TC) and the source of the N-channel field effect transistor (R2 is connected to source of TR) but does not disclose P-channel transistors.
Miyaoka discloses in place of the CMOS circuit, furthermore, either the n-channel MOSFETs or p-channel MOSFETs may be employed for the purpose of realizing the circuit in a variety of ways (Miyaoka, Col 11 Lines 14-18).
Since Lin and Miyaoka are both from the same field of endeavor (Accessing non-volatile memory), the purpose disclosed by Miyaoka would have been recognized in the pertinent art of Lin.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to use n or p transistors as taught by Miyaoka in the circuit taught by Lin for the purposes of realizing the circuit in a variety of ways.
Claim 2. The storage array according to claim 1, wherein the memory cell comprises a first N-channel field effect transistor (TL, Lin Fig 7A), a first P-channel field effect transistor (TC), and a second N-channel field effect transistor connected in sequence (TR); wherein gates of the first N-channel field-effect transistor (at WL2L), the second N-channel field-effect transistor (at WL2R), and the first P-channel field-effect transistor (at WL2) are connected to different word lines respectively (as shown in Fig 7A), and a source of the first N-channel field-effect transistor and a source of the second N-channel field-effect transistor are connected to different source lines respectively (SL2L and SL2R respectively, Lin Fig 7A).
Claim 3. The storage array according to claim 2, wherein a source line is configured to (configured to is functional language) be connected to a positive voltage VDD (SL2L is configured to be connected to VDD during a logic high value), a saturation current of the first P-channel field effect transistor is represented as follows: Imax=(Kw/L)p*(Vsg-Vtp)2, where Vsg = Vs< VDD (Vsg is 0 thus smaller than VDD), and (Kw/L)p and Vtp represent inherent parameters of the first P-channel field effect transistor, Vsg represents a source-gate voltage of the first P-channel field effect transistor, Vs represents a source voltage of the first P-channel field effect transistor (as seen in Fig 7A).
Claim 4. The storage array according to claim 2, wherein the memories comprise a first memory and a second memory (R1 and R2, Lin Fig 7A), the first memory is configured to (configured to is functional language) be connected to the source of the first P-channel field effect transistor (R1 is connected to TC), and the second memory is configured to (configured to is functional language) be connected to the source of the second N-channel field effect transistor (R2 is connected to TR).
Claim 5. The storage array according to claim 2, comprising M × N memory cells, wherein M represents the number of rows, N represents the number of columns (as seen in Fig 1), the word lines comprise a word line N connected to gates of the N-channel field effect transistors (WL0L connected to gate of TL fig 7A) and a word line P connected to a gate of the P-channel field effect transistor (WL0 connected to gate of TC fig 7A), wherein the memory cells in the same row are configured to (configured to is functional language) share the word line N and a bit line (the memory cells in the same row are configured to share word line WL0L and a bitline BL0), and memory cells in the same column are configured to (configured to is functional language) share the word line P and a source line (WL0 and SL0L).
Claim 6. The storage array according to claim 5, comprising a storage mode, a write-1 mode, a write-0 mode, and a read mode (array of memory cells comprising R1 and R2 comprise a storage mode, a write-1 mode, a write-0 mode, and a read mode, Lin Fig 1); wherein in the storage mode, each memory cell is configured to (configured to is functional language) be in a non-operating state and maintain original data thereof; in the write-1 mode and the write-0 mode (cells comprising R1 and R2 are configured to be in a non-operating state and maintain original data thereof; in the write-1 mode and the write-0 mode), specified memory cells are configured to (configured to is functional language) be in a state-1 and a state-0 respectively, wherein voltages of the specified memory cells are less than a preset voltage VDD (R1 and R2 can be in 1 or 0 state when writing, 0V is less than VDD); and in the read mode, a source line of a memory (SL0L) cell is configured to (configured to is functional language) be connected to a read voltage (voltage on SL0L) to allow a read current to reach a bit line (BL0) through the memory cell (R1) and to read a corresponding state of the memory cell from the bit line (BL0).
Claim 7. The storage array according to claim 6, wherein in the storage mode, all the word lines N, the bit lines, and the source lines are configured to (configured to is functional language) be connected to GND (all the word lines N, the bit lines, and the source lines are configured to connected to GND through SLs and BLs, Lin Fig 4), and the word line P is configured to (configured to is functional language) be connected to the preset voltage VDD (WL0 Fig 4 is configured to be connected to a preset voltage on BL0); and the P-channel field effect transistor and the N-channel field effect transistors are configured to (configured to is functional language) be in an off state (OFF states taught in Fig 4).
Claim 8. The storage array according to claim 6, wherein in the write-1 mode, the word line N is configured to (configured to is functional language) be connected to the preset voltage VDD (configured to be connected to the preset voltage VDD through SL0L), and the word line P is configured to (configured to is functional language) be connected to the GND (WL0 configured to be coupled to 0V shown in, Lin Fig 4); after a target memory cell is strobed (comprising R1), a source line of the target memory cell is configured to (configured to is functional language) be connected to a preset write-1 voltage (SL0L configured to be connected to a preset write-1 voltage when writing), a target bit line of the target memory cell is configured to (configured to is functional language) be connected to the GND (BL0 is configured to be coupled to 0V), the rest of the bit lines are configured to (configured to is functional language) be connected to the write-1 voltage (other BLs are configured to be connected to the write-1 voltage as seen in Fig 1), and the target memory cell is configured to (configured to is functional language) be written to the state-1 (R1 cell is configured to be written to the state-1).
Claim 9. The storage array according to claim 6, wherein in the write-0 mode, the word line N is configured to (configured to is functional language) be connected to the preset voltage VDD (read preset voltage VDD is passed through SL0L, Lin Fig 1, when reading), the word line P and the source line are configured to (configured to is functional language) be connected to the GND (SL0L Coupled to GND Fig 3A); and after a target memory cell is strobed (comprising R1), a bit line of the target memory cell is configured to (configured to is functional language) be connected to a preset write-0 voltage (BL0 is configured to be coupled to 0V), source lines of other memory cells are configured to (configured to is functional language) be connected to the preset write-0 voltage (SLs are configured to be connected to the preset write-0 voltage as seen in Fig 3A), a write current flows from the bit line (BL0) through the target memory cell (R1) to the source line (SL0L), and the target memory cell is configured to (configured to is functional language) be written to the state-0 (R1 is configured to be written to the state-0).
Claim 10. The storage array according to claim 6, wherein in the read mode, the word line N is configured to (configured to is functional language) be connected to the preset voltage VDD (configured to be connected to VDD at input when accessing the line), and the source line is configured to (configured to is functional language) be connected to the read voltage (SL0L, Lin Fig 1 is configured to be connected the read voltage to read R1, on left); and after a target memory cell is strobed (comprising R1), a read current flows from the source line (SL0L, Lin Fig 1) through the target memory cell (R1) to the bit line (BL0), and a corresponding state of the memory cell is read from the bit line (state of memory cell is read from BL0).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Lappas whose telephone number is (571) 270-1272. The examiner can normally be reached on M-F 7:30AM-5:00PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON LAPPAS/
Primary Examiner, Art Unit 2827