DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/15/2026 has been entered. Claims 1-8 are currently pending in the application. An action follows below:
Response to Arguments
The rejections under 35 U.S.C. 112(a) and 35 U.S.C. 112(b) in the previous Office action dated 04/29/2026 have been withdrawn in light of the amendment to this claim.
In response to the rejections of claims 1-8 under 35 U.S.C. 103 as being unpatentable over in view of Kim in view of Sasaki in the previous Office action, Applicant has provided an argument: “… the first transistor 474 is integral to pixel 430, and implementation of the transistor l0E depicted in FIGS. 49 and 50, as described by Sasaki, would also result in an integral incorporation in the pixel 430. Thus, Sasaki fails to describe or suggest a transistor structure in a circuit different from a pixel … in claim 1 …” (see pages 7-8 of the amendment.) Examiner respectfully disagrees because the modified Kim is to implement the first transistor of the Kim reference with the detailed structure of an oxide semiconductor transistor, taught by the Sasaki reference, itself capable of improving the mobility of the transistor and increasing the ratio and thus decreasing the influent of light.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-8 are rejected under 35 U.S.C. 112(a), as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Note that, in order to satisfy its burden under the written description requirement, a patent application must disclose the full scope of the claim. Univ. of Rochester v. G.D. Searle & Co., 358 F.3d 916, 920 (Fed. Cir. 2004) (The purpose of the written description requirement is to “ensure that the scope of the right to exclude, as set forth in the claims, does not overreach the scope of the inventor’s contribution to the field of art as described in the patent specification.”.)
As per claim 1, this claim recites a limitation, “wherein the first transistor comprises a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a second insulating layer” in lines 10-11, which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor(s), at the time the application was filed, had possession of the claimed invention. The original disclosure, specifically Fig. 2B, discloses the first transistor [33] comprising a portion of a first conductive layer [111], a portion of a second conductive layer [112], a portion of a third conductive layer [115], a portion of a semiconductor layer [113], and a portion of a second insulating layer [105]. However, the original disclosure does not explicitly discuss in detail the first transistor [33] comprising a whole first conductive layer [111], a whole second conductive layer [112], a whole third conductive layer [115], a whole semiconductor layer [113], and a whole second insulating layer [105], of the above underlined limitation, so as to reasonably convey to one skilled in the relevant art that the inventor(s), at the time the application was filed, had possession of the claimed invention. Further, see the above bolded note.
As per claims 2 and 7, these claims are therefore rejected for at least the reason set forth in claim 1 above.
As per claim 3, this claim recites limitations, “wherein the first transistor comprises a first conductive layer, a second conductive layer, a third conductive layer, a first semiconductor layer, and a second insulating layer, wherein the second transistor comprises the second conductive layer, a fourth conductive layer, a fifth conductive layer, a second semiconductor layer, and the second insulating layer” in lines 12-15, which were not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor(s), at the time the application was filed, had possession of the claimed invention. The original disclosure, specifically Fig. 4B, discloses the first transistor (33[1]) comprising a portion of a first conductive layer (111[1]), a portion of a second conductive layer (112[1]), a portion of a third conductive layer (115[1]), a portion of a first semiconductor layer (113[1]), and a portion of a second insulating layer (105); and the second transistor (33[2]) comprising a portion of the second conductive layer (112[1]), a portion of a fourth conductive layer (112[2]), a portion of a fifth conductive layer (115[2]), a portion of a second semiconductor layer (113[2]), and a portion of the second insulating layer (105). However, the original disclosure does not explicitly discuss in detail the first transistor (33[1]) comprising a whole first conductive layer (111[1]), a whole second conductive layer (112[1]), a whole third conductive layer (115[1]), a whole first semiconductor layer (113[1]), and a whole second insulating layer (105); and the second transistor (33[2]) comprising a whole second conductive layer (112[1]), a whole fourth conductive layer (112[2]), a whole fifth conductive layer (115[2]), a whole second semiconductor layer (113[2]), and a whole second insulating layer (105), of the above underlined limitation, so as to reasonably convey to one skilled in the relevant art that the inventor(s), at the time the application was filed, had possession of the claimed invention. Further, see the above bolded note.
As per claims 4 and 8, these claims are therefore rejected for at least the reason set forth in claim 3 above.
As per claim 5, see the rejection of claim 3 for similar limitations.
As for claim 6, this claim is therefore rejected for at least the reason set forth in claim 5 above.
Notice to Applicant(s)
Examiner notes that the specification is not the measure of invention. Therefore, limitations contained therein can’t be read into the claims for the purpose of avoiding the prior art. See In re Sporck, 55 CCPA 743, 386 F.2d 924, 155 USPQ 687 (1968).
Further, the names/ terms of the features/elements used in the pending application or pending claims may be different from the names/terms of the matching features/ elements of the prior arts; however, the matching features/ elements of the prior arts contain all characteristics/ functions of the features/elements DEFINED by the pending claims.
Note that in order to avoid confusion, the below citations in the below rejection(s) are mere one or more places in the reference to disclose the "claimed" limitation(s) and/or are directed to one or more of embodiments disclosed by the cited reference(s). In other words, the “claimed” features/limitations may be read in other places in the reference or other embodiments of the reference. In order to better understand how the claimed limitations are taught by the reference(s), a review of the entire reference(s) is suggested by the examiner. Applicant is reminded a prior art reference must be considered in its entirety, i.e., as a whole, including portions that would lead away from the claimed invention as not all relevant paragraphs may have been cited in the rejection. W.L. Gore & Associates, Inc. v. Garlock, Inc., 721 F.2d 1540, 220 USPQ 303 (Fed. Cir. 1983), cert. denied, 469 U.S. 851 (1984).
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over in view of Kim et al. (US 2006/0107146 A1; hereinafter Kim) in view of Sasaki (US 2017/0271375 A1.)
As per claim 1, Kim discloses a display apparatus (see at least Fig. 2) comprising:
a signal line driver circuit [120; Fig. 2];
a circuit comprising a first transistor (see at least Figs. 2, 5, disclosing a circuit [162/ 160] comprising a first transistor [T1];) and
a pixel comprising a display element and a second transistor electrically connected to the display element (see at least Figs. 2, 5, disclosing a circuit [162/ 160] comprising a first transistor [T1], and a pixel [140/ 142R/ 142G/ 142B] comprising a display element [OLED] and a second transistor [M2] electrically connected to the display element,)
wherein the signal line driver circuit is electrically connected to an input terminal of the circuit (see at least Fig. 2, disclosing the signal line driver circuit [120] electrically connected to an input terminal of the circuit [162/ 160] via a line [D1/ D2/ …Dm/i],)
wherein an output terminal of the circuit is electrically connected to the pixel (see at least Figs. 2, 5, disclosing, an output terminal of the circuit [162/ 160] electrically connected to the pixel [140/ 142R/ 142G/ 142B] via a line [DL1/ DL2/ …DLm],)
wherein see at least Figs. 2, 5,) and
wherein see at least Figs. 2, 5.)
Accordingly, Kim discloses all limitations of this claim except that Kim is silent to a particular structure of the first transistor, as claimed.
However, in the same field of endeavor, Sasaki discloses a related display apparatus (see at least Figs. 309-311 and 49-50 used in the display device of Fig. 309 at ¶¶ 765, 766, 784, disclosing a related display device/apparatus) utilizing a first transistor [474/10E] (see at least Figs. 309, 311, disclosing, e.g., a transistor [474/10E]) comprising: a first insulating layer [130E], a first conductive layer [444/120E], a second conductive layer [452/140E], a third conductive layer [460/180E], an oxide semiconductor layer [504/160E] formed of a metal oxide material (see at least ¶ 352,) and a second insulating layer [170E] (see at least Figs. 311, 50,)
wherein the first insulating layer [130E] is over the first conductive layer [444/120E] (see at least Figs. 311, 50,)
wherein the second conductive layer [452/140E] is over the first insulating layer [130E] (see at least Figs. 311, 50,)
wherein the first insulating layer [130E] comprises a first opening reaching the first conductive layer [444/120E] (see at least Figs. 311, 50,)
wherein the second conductive layer [452/140E] comprises a second opening comprising a region overlapping with the first opening (see at least Figs. 311, 50,)
wherein the semiconductor layer [504/160E] comprises a region in contact with the first conductive layer [440/120E] and a region in contact with the second conductive layer [452/140E] and comprises a region in the first opening and a region in the second opening (see at least Figs. 310, 50; also see Figs. 311 and 50 for another transistor, if necessary,)
wherein the second insulating layer [170E] is over the semiconductor layer [504/160E] to comprise a region in the first opening and a region in the second opening (see at least Figs. 311, 50,)
wherein the third conductive layer [460/180E] is over the second insulating layer [170E] to comprise a region in the first opening and a region in the second opening (see at least Figs. 311, 50,)
wherein the first conductive layer [444/120E] including an output terminal/electrode of the first transistor [474/10E] is electrically connected to the pixel (see at least Figs. 309, 311, 50; ¶¶ 771-772,) and
wherein the second conductive layer [452/140E] including an input terminal/electrode of the first transistor [474/10E] is electrically connected to the signal line driver circuit (see at least Fig. 309; ¶¶ 3-5, 766, disclosing a signal line driver circuit providing signals to drive a plurality of data lines [440, 450, 452 …]; further see at least Figs. 309, 311, 50; ¶¶ 771-772, disclosing the second conductive layer [452/140E] electrically connected to the signal line driver circuit.)
Sasaki further discloses that the first transistor comprising the oxide semiconductor layer [504/160E] formed of a metal oxide material, as discussed above, improves the mobility of the transistor, increases the ratio and thus decreases the influent of light (see at least ¶ 352; further see ¶ 457 for other benefits.)
Thus, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of invention of the pending application to implement the first transistor of the Kim reference with the detailed structure of an oxide semiconductor transistor taught by the Sasaki reference, to improve the above modified display apparatus of the Kim reference for the predictable result of improving the mobility of the transistor, increasing the ratio, and thus decreasing the influent of light. Accordingly, the above modified Kim in view of Sasaki obviously renders all limitations of this claim.
As per claim 2, the above modified Kim in view of Sasaki obviously renders the semiconductor layer comprising a metal oxide (see Sasaki at least ¶ 352, disclosing the semiconductor layer [504/160] comprising a metal oxide.)
As per claim 3, see the rejection of claim 1 for similar limitations. Note that “a third transistor” of claim 3 corresponds to “a second transistor” of claim 1. Kim further discloses the display device comprising a plurality of pixels [140/ 142] in the gate line direction and in the data line direction, including a second pixel [140/142G] (see Kim at least Figs. 2, 5,) wherein the circuit 162/160] further includes a second transistor [T2] (see Kim at least Figs. 2, 5,) wherein the first pixel [140/ 142R] and the second pixel [140/ 142G] each comprise a display element [OLED] and a third transistor [M2] electrically connected to the display element (see Kim at least Fig. 5,) wherein the signal line driver circuit [120] is electrically connected to an input terminal of the circuit [162/160] (see the discussion in rejection of claim 1; or see Kim at least Figs. 2, 5,) wherein an output terminal of the circuit [162/160] is electrically connected to the pixel (see the discussion in rejection of claim 1; or see Kim at least Figs. 2, 5.) Note that the claimed second transistor [T2 of Kim] has the same structure as the claimed first transistor [T1 of Kim] and the detailed structure of the claimed first transistor discussed in the rejection of claim 1. Accordingly, the above modified Kim in view of Sasaki obviously renders all limitations of this claim.
As per claim 4, the above modified Kim in view of Sasaki obviously renders the first semiconductor layer and the second semiconductor layer each comprise a metal oxide (see the rejection of claims 1 and 3 for the first semiconductor layer and the second semiconductor layer ; and further Sasaki at least ¶ 352, disclosing semiconductor layer comprising a metal oxide.)
As per claim 5, see the rejection of claims 1 and 3 for similar limitations. Note that while Kim exemplifies in Fig. 5 that each demultiplexer [162] comprising three transistors [T1-T3], Kim, at least Fig. 2 and ¶ 44, further discloses each demultiplexer [162] comprising three or more transistors, thereby obviously rendering each demultiplexer [162] comprising four or more transistors. In other words, Kim obviously discloses the claimed circuit [162/ 160] comprising a first transistor [T1], a second transistor [T2], a third transistor [T3], and a fourth transistor [T4]. Kim further discloses a first pixel [140/142R], a second pixel [140/142G], a third pixel [140/142B], and a fourth pixel [140/142R] disposed in a row and each comprise a display element and a fifth transistor electrically connected to the display element (see at least Figs. 2 and 5; note that “a fifth transistor” of claim 5 corresponds to “a third transistor” of claim 3 or “a second transistor” of claim 1,) wherein the signal line driver circuit [120] is electrically connected to an input terminal of the circuit [162/160] (see the discussion in rejection of claim 1; or see Kim at least Figs. 2, 5,) wherein an output terminal of the circuit [162/160] is electrically connected to the pixel (see the discussion in rejection of claim 1; or see Kim at least Figs. 2, 5.) Note that each of the second, third and fourth transistors of Kim has the same structure as the claimed first transistor and the detailed structure of the claimed first transistor discussed in the rejection of claim 1. Accordingly, the above modified Kim in view of Sasaki obviously renders all limitations of this claim.
As per claim 6, the above modified Kim in view of Sasaki obviously renders the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer to fourth semiconductor layers each comprising a metal oxide (see the rejection of claims 1 and 5 for the first to fourth semiconductor layers; and further Sasaki at least ¶ 352, disclosing semiconductor layer comprising a metal oxide.)
As per claim 7, the above modified Kim in view of Sasaki obviously renders the metal oxide comprising indium, zinc, and M, and wherein M is one kind selected from aluminum, titanium, gallium, germanium, tin, yttrium, zirconium, lanthanum, cerium, neodymium, and hafnium (see Sasaki discloses at paragraph [0352] “… the oxide semiconductor layer 160 may be formed of an oxide semiconductor containing indium (In), gallium (Ga), Zinc (Zn) and oxygen (O) …”
As per claim 8, the above modified Kim in view of Sasaki, as discussed in the rejection of claim 3, obviously renders the display apparatus further comprising a control circuit (see Kim at least Fig. 2, disclosing a control circuit including at least a demultiplexer controller 170,) wherein the control circuit is configured to generate a first signal [Cs1] and output the first signal to the third conductive layer (see Kim at least Figs. 2, 5; further see the discussion in the rejection of claims 1 and 3, whereat the above modified Kim in view of Sasaki, as discussed in the rejection of claim 3, obviously renders the third conductive layer including a gate electrode of the first transistor [T1]) and wherein the control circuit is configured to generate a second signal [CS2] and output the second signal to the fifth conductive layer (see Kim at least Figs. 2, 5; further see the discussion in the rejection of claims 1 and 3, whereat the above modified Kim in view of Sasaki, as discussed in the rejection of claim 3, obviously renders the fifth conductive layer including a gate electrode of the second transistor [T2].)
Kim further exemplifies, in the case of each demultiplexer [162] providing three signals [CS1-CS3], one of the three signals has a low level signal to turn on the corresponding transistor and others of the three signals has a high level signal to turn off the corresponding transistors (see at least Figs. 5-6.) Kim further discloses the case that each demultiplexer [162] provides two signals [CS1-CS2] when “i = 2” (see at least ¶ 44.) Based on these teachings, a person having an ordinary skill in the display art would have readily recognized that in the case of “i = 2”, i.e., each demultiplexer [162] providing two signals [CS1-CS2], the first signal has a low level signal to turn on the first transistor [T1] and the second signal has a high level signal to turn off the second transistor [T2] during the data writing period, thereby obviously rendering the first signal and the second signal being signals complementary to each other.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jimmy H Nguyen whose telephone number is (571) 272-7675. The examiner can normally be reached on Monday-Friday 8:30AM-6PM.
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/Jimmy H Nguyen/
Primary Examiner, Art Unit 2626
Prosecution Insights