DETAILED ACTION
Specification
1. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
2. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1 - 3, 16 – 19, 21 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (20240038948) in view of Jung et al. (11844237).
With regard to claim 1, Cheng et al. disclose a wiring substrate (for example, see figs. 2A, 3), comprising:
a base substrate (substrate layers 1, 2 functions as a base substrate or layer 14 functions as a base substrate) comprising a first surface (a substrate 1 having a first surface) and a second surface (a substrate 2 having a second surface) arranged oppositely,
wherein the second surface (the substrate 2 having the second surface) comprises a bonding region (a chip region 3, having bonding terminals 203, functions as a bonding region) extending in a first direction (for example, X-direction as shown in fig. 3) and fan-out
regions (200a, 200b) located on both sides of the bonding region (3) in a second direction (for example, Y-direction as shown in fig. 3),
the fan-out regions (200a, 200b) are provided with a plurality of vias (12), and the first direction (for example, X-direction as shown in fig. 3) intersects the second direction (for example, Y-direction as shown in fig. 3);
a plurality of signal lines (1071c, or 1071a, 1071b) on the first surface, wherein orthographic projections of the plurality of signal lines (1071c, or 1071a, 1071b) on the base substrate (substrate layers 1, 2 functions as a base substrate or layer 14 functions as a base substrate); and
a plurality of connection lines (201) on the second surface (the substrate 2 having the second surface), wherein the plurality of connection lines (201) extend from the fan-out regions (200a, 200b) to the bonding region (the chip region 3, having bonding terminals 203, functions as the bonding region), and
the plurality of connection lines (201 or 203) are coupled with the plurality of signal lines (1071c, or 1071a, 1071b) through the plurality of vias (12).
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Cheng et al. do not clearly disclose orthographic projections of the plurality of signal lines on the base substrate extend in the second direction, passing through the bonding region and the fan-out regions.
However, Jung et al. disclose orthographic projections of the plurality of signal lines (data lines DL functions as signal lines) on the base substrate (100) extend in the second direction (for example, Y-direction as shown in fig. 8), passing through the bonding region (PAD region) and the fan-out regions (referred to as “FW1” by examiner’s annotation shown in fig. 8 below; wherein the fan-out regions FW1 having fan-out wires FW).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Cheng et al.’s device to have orthographic projections of the plurality of signal lines on the base substrate extend in the second direction, passing through the bonding region and the fan-out regions as taught by Jung et al. in order to generate a high efficiency of a data signal, and the generated data signal may be transmitted to the pixel circuits for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 2, Cheng et al. disclose the bonding region (the chip region 3, having bonding terminals 203, functions as the bonding region) is located in a middle region of the second surface (the substrate 2 having the second surface).
With regard to claim 3, Jung et al. disclose the fan-out regions (FW1) on both sides of the bonding region (PAD) are indicated as a first fan-out region and a second fan-out region, respectively; the plurality of connection lines (11, 13) comprise a constant voltage signal connection line (the driving voltage ELVDD or 11 functions as a constant voltage signal connection line) and a common voltage signal connection line (13); the constant voltage signal connection line (11) extends from the first fan-out region (FW1) to the bonding region (PAD), and the common voltage signal connection line (13) extends from the second fan-out
region (FW2) to the bonding region (PAD).
With regard to claim 16, Cheng et al. disclose an insulating layer (22) on a side of the plurality of connection lines (203) away from the base substrate (layer 14 functions as the base substrate) wherein the insulating layer (22) comprises a plurality of openings (referred to as “OP” by examiner’s annotation shown in fig. 2A below) in the bonding region, and in
the bonding region, orthographic projections (referred to as “203A” by examiner’s annotation shown in fig. 2A below) of some of the plurality of connection lines (1071c) on the
base substrate (14) are located within orthographic projections of the plurality of openings (OP) on the base substrate (14).
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With regard to claim 17, Cheng et al. disclose a plurality of light-emitting structures (101) coupled with the plurality of signal lines (1071c, or 1071a, 1071b).
With regard to claim 18, Cheng et al. disclose the first surface comprises a plurality of pad regions (111, 112, 1072); wherein the pad region is provided with a first pad group and a second pad group, the light-emitting structure (110) is an electronic component coupled with the first pad group (111, 112) and a micro drive chip (a drive chip 10, forming in the micro panel, functions as a micro drive chip; for example, see paragraph [0068]) coupled with the second pad group (1072).
With regard to claim 19, Cheng et al. disclose a drive circuit board (a board having a chip 3); wherein the drive circuit board is coupled with the plurality of connection lines (201) in the
bonding region; wherein the drive circuit board (the board having the chip 3) functions as a chip-on-film (COF).
With regard to claim 21, Cheng et al. disclose a manufacturing method for a wiring substrate (for example, see figs. 2A, 3), comprising:
providing a base substrate (substrate layers 1, 2 functions as a base substrate or layer 14 functions as a base substrate); wherein the base substrate comprises a first surface (a substrate 1 having a first surface) and a second surface (a substrate 2 having a second surface) arranged oppositely,
the second surface (the substrate 2 having the second surface) comprises a bonding region (a chip region 3, having bonding terminals 203, functions as a bonding region) extending in a first direction (for example, X-direction as shown in fig. 3) and fan-out regions (200a, 200b) located on both sides of the bonding region (3) in a second direction (for example, Y-direction as shown in fig. 3), and the first direction (for example, X-direction as shown in fig. 3) intersects the second direction (for example, Y-direction as shown in fig. 3);
forming a plurality of vias (12) at predetermined positions in the fan-out regions (200a, 200b), wherein the plurality of vias (12) pass through the base substrate (substrate layers 1, 2 functions as a base substrate or layer 14 functions as a base substrate) in a direction perpendicular to the first surface and the second surface;
forming a plurality of signal lines (1071c, or 1071a, 1071b) on the first surface; wherein orthographic projections of the plurality of signal lines (1071c, or 1071a, 1071b) on the base substrate (substrate layers 1, 2 functions as a base substrate or layer 14 functions as a base substrate),
; forming a plurality of connection lines (201), extending from the fan-out regions (200a, 200b) to the bonding region (the chip region 3, having bonding terminals 203, functions as the bonding region), on the second surface, in such a way that the plurality of connection lines (201) are coupled with the plurality of signal lines (1071c, or 1071a, 1071b) through the plurality of vias (12).
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Cheng et al. do not clearly disclose orthographic projections of the plurality of signal lines on the base substrate extend in the second direction, passing through the bonding region and the fan-out regions.
However, Jung et al. disclose orthographic projections of the plurality of signal lines (data lines DL functions as signal lines) on the base substrate (100) extend in the second direction (for example, Y-direction as shown in fig. 8), passing through the bonding region (PAD region) and the fan-out regions (referred to as “FW1” by examiner’s annotation shown in fig. 8 below; wherein the fan-out regions FW1 having fan-out wires FW).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Cheng et al.’s device to have orthographic projections of the plurality of signal lines on the base substrate extend in the second direction, passing through the bonding region and the fan-out regions as taught by Jung et al. in order to generate a high efficiency of a data signal, and the generated data signal may be transmitted to the pixel circuits for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
4. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (20240038948) in view of Jung et al. (11844237) and further in view of Lee et al. (12074155).
With regard to claim 15, Cheng et al. and Jung et al. do not clearly disclose the first surface comprises 2n *2m pad regions, and n and m are integers greater than 2; the pad region is provided with a first pad group and a second pad group, and the first pad group comprises at least two sub-pad groups; in at least a 2n-th row of pad regions, the second pad group is located between adjacent sub-pad groups of the at least two sub-pad groups.
However, Lee et al. disclose the first surface comprises 2n *2m pad regions (2210B, 2220B, 2230B) and n and m are integers greater than 2; the pad region is provided with a first pad group (referred to as “223A” by examiner’s annotation shown in fig. 4 below) and a second pad group (referred to as “223B” by examiner’s annotation shown in fig. 4 below), and the first pad group (223A) comprises at least two sub-pad groups (referred to as “A1” by examiner’s annotation shown in fig. 4 below); in at least a 2n-th row (referred to as “223C” by examiner’s annotation shown in fig. 4 below) of pad regions (2210B, 2220B, 2230B), the second pad group (223B) is located between adjacent sub-pad groups of the at least two sub-pad groups (A1).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Cheng et al.’s device to have the first surface comprises 2n *2m pad regions, and n and m are integers greater than 2; the pad region is provided with a first pad group and a second pad group, and the first pad group comprises at least two sub-pad groups; in at least a 2n-th row of pad regions, the second pad group is located between adjacent sub-pad groups of the at least two sub-pad groups as taught by Jung et al. in order to secure electrical connection efficiency of the devices for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Allowable Subject Matter
5. Claims 4 - 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 4 - 14 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as the constant voltage signal connection line comprises a first constant voltage signal connection part extending in the second direction, and the common voltage signal connection line comprises a first common voltage signal connection part extending in the second direction; the first constant voltage signal connection part extends from the first fan-out region to the bonding region, and the first common voltage signal connection part extends from the second fan-out region to the bonding region, and the first common voltage signal connection part and the first constant voltage signal connection part are staggered in the first direction as recited in claim 4.
Conclusion
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812
Prosecution Insights