Prosecution Insights
Last updated: October 25, 2026
Application No. 18/852,619

SEMICONDUCTOR DEVICE

Non-Final OA §102
Filed
Sep 30, 2024
Priority
Apr 15, 2022 — JP 2022-067447 +1 more
Examiner
ANYA, IGWE U
Art Unit
Tech Center
Assignee
Semiconductor Energy Laboratory Co., Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
820 granted / 964 resolved
+25.1% vs TC avg
Minimal -4% lift
Without
With
+-3.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
29 currently pending
Career history
998
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
50.9%
+10.9% vs TC avg
§102
36.8%
-3.2% vs TC avg
§112
7.0%
-33.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 964 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 – 6, 8 – 13, 15 – 17 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Miyairi (US 2016/0233343). PNG media_image1.png 203 375 media_image1.png Greyscale PNG media_image2.png 270 261 media_image2.png Greyscale (Claim 1) Miyairi teaches a semiconductor device (fig. 2 and using fig. 1 for nomenclature) comprising: a first insulating layer (120); a semiconductor layer (130); a gate insulating layer (160); a gate electrode (170b); a first electrode (140); a second electrode (150); and a first conductive layer (170a or 170a+183), wherein a side surface of the first insulating layer (120) is over the first electrode (140), wherein the second electrode (150) is over the first insulating layer (120), wherein the semiconductor layer (130) is in contact with the first electrode (140), the side surface of the first insulating layer (120), and the second electrode (150), wherein the gate insulating layer (160) comprises a portion facing the side surface of the first insulating layer (120) with the semiconductor layer (130) interposed between the first insulating layer (120) and the gate insulating layer (160), wherein the gate electrode (170b) comprises a portion facing the side surface of the first insulating layer (120) with the gate insulating layer (160) and the semiconductor layer (130) interposed between the first insulating layer (120) and the gate electrode (170b), wherein the first conductive layer (170a/183) is in contact with the gate electrode (170b), wherein the first conductive layer (170a/183) comprises a portion facing the side surface of the first insulating layer (120) with the gate electrode (170b), the gate insulating layer (160), and the semiconductor layer (130) interposed between the first insulating layer (120) and the first conductive layer (170a/183), and wherein the first conductive layer (170a/183) comprises a portion thicker than the gate electrode (170b). (Claim 2) Miyairi teaches a semiconductor device comprising: a first insulating layer (120); a semiconductor layer (130); a gate insulating layer (160); a gate electrode (170b); a first electrode (140); a second electrode (150); and a first conductive layer (170a/183), wherein the first insulating layer (120) comprises an opening, wherein a side surface of the first insulating layer (120) in the opening is over the first electrode (140), wherein the second electrode (150) is over the first insulating layer (120), wherein the semiconductor layer (130), the gate insulating layer (160), the gate electrode (170b), and the first conductive layer (170a/183) each comprises a portion inside the opening, wherein the semiconductor layer (130) is in contact with the first electrode (140), the side surface of the first insulating layer (120), and the second electrode (150), wherein the gate insulating layer (160) comprises a portion facing the side surface of the first insulating layer (120) with the semiconductor layer (130) interposed between the first insulating layer (120) and the gate insulating layer (160), wherein the gate electrode (170b) comprises a portion facing the side surface of the first insulating layer (120) with the gate insulating layer (160) and the semiconductor layer (13) interposed between the first insulating layer (120) and the gate electrode (170b), wherein the first conductive layer (170a/183) is in contact with the gate electrode (170a), wherein the first conductive layer (170a/183) comprises a portion facing the side surface of the first insulating layer (120) with the gate electrode (170b), the gate insulating layer (160), and the semiconductor layer (130) interposed between the first insulating layer (120) and the first conductive layer (170a/183), and wherein the first conductive layer (170a/183) comprises a portion thicker than the gate electrode (170b). (Claim 3) Miyairi teaches a semiconductor device comprising: a first insulating layer (120); a semiconductor layer (130); a gate insulating layer (160); a gate electrode (170b); a first electrode (140); a second electrode (150); and a first conductive layer (170a/183), wherein the first insulating layer (120) comprises a slit, wherein a side surface of the first insulating layer (120) in the slit is over the first electrode (140), wherein the second electrode (150) is over the first insulating layer (120), wherein the semiconductor layer (130), the gate insulating layer (160), the gate electrode (170b), and the first conductive layer (170a/183) each comprise a portion inside the slit, wherein the semiconductor layer (130) is in contact with the first electrode (140), the side surface of the first insulating layer (120), and the second electrode (150), wherein the gate insulating layer (160) comprises a portion facing the side surface of the first insulating layer (120) with the semiconductor layer (130) interposed between the first insulating layer (120) and the gate insulating layer (160), wherein the gate electrode (170b) comprises a portion facing the side surface of the first insulating layer (120) with the gate insulating layer (160) and the semiconductor layer (130) interposed between the first insulating layer (120) and the gate electrode (170b), wherein the first conductive layer (170a/183) is in contact with the gate electrode (170a), wherein the first conductive layer (170a/183) comprises a portion facing the side surface of the first insulating layer (120) with the gate electrode (170b), the gate insulating layer (160), and the semiconductor layer (130) interposed between the first insulating layer (120) and the first conductive layer (170a/183), and wherein the first conductive layer (170a/183) comprises a portion thicker than the gate electrode (170b). (Claim 4) Miyairi teaches the semiconductor device, further comprising a second insulating layer (125), wherein a top surface of the first conductive layer (170a/183) is level or substantially level with a top surface of the second insulating layer (125). (Claim 5) Miyairi teaches wherein the semiconductor layer (130) comprises a metal oxide (paragraph 74), and wherein the first electrode (140) comprises a metal oxide having a composition different from that of the semiconductor layer (paragraph 119). (Claim 6) Miyairi teaches the semiconductor device, further comprising a second conductive layer (fig. 1 C #181), wherein the first electrode (140) comprises a portion in contact with a top surface of the second conductive layer (181), and wherein the second conductive layer (181) comprises a metal or an alloy (paragraph 118). (Claim 8) Miyairi teaches wherein an angle formed between the side surface of the first insulating layer (120) and a top surface of the first electrode (140) is greater than or equal to 90 degrees and less than or equal to 120 degrees. (Claim 9) Miyairi teaches wherein the side surface of the first insulating layer (120) comprises an uneven shape (bottom notch). (Claim 10) Miyairi teaches wherein the semiconductor layer (130) is in contact with a top surface of the second electrode (150), wherein the semiconductor layer (130) comprises a metal oxide (paragraph 74, 134), and wherein the second electrode (160) comprises a metal oxide having a composition different from that of the semiconductor layer (paragraph 130). (Claim 11) Miyairi teaches the semiconductor device, further comprising a third conductive layer (182), wherein the second electrode (150) comprises a portion (top) in contact with the third conductive layer (182), and wherein the third conductive layer (182) comprises a metal or an alloy (paragraph 162). (Claim 12) Miyairi teaches wherein the semiconductor layer (130) comprises a metal oxide (paragraphs 74, 134), and wherein the first electrode (140) comprises a metal oxide having a composition different from that of the semiconductor layer (paragraph 119). (Claim 13) Miyairi teaches the semiconductor device, further comprising a second conductive layer (fig. 1C #181), wherein the first electrode (140) comprises a portion (bottom) in contact with a top surface of the second conductive layer (181), and wherein the second conductive (181) layer comprises a metal or an alloy (paragraph 118). (Claim 15) Miyairi teaches wherein the semiconductor layer (130) is in contact with a top surface of the second electrode (150), wherein the semiconductor layer comprises (130) a metal oxide (paragraphs 74, 134), and wherein the second electrode (150) comprises a metal oxide (paragraph 130) having a composition different from that of the semiconductor layer. (Claim 16) Miyairi teaches wherein the semiconductor layer (130) comprises a metal oxide (paragraphs 74, 134), and wherein the first electrode (140) comprises a metal oxide (paragraph 119) having a composition different from that of the semiconductor layer. (Claim 17) Miyairi teaches the semiconductor device, further comprising a second conductive layer (fig. 1C #181), wherein the first electrode (140) comprises a portion (bottom) in contact with a top surface of the second conductive layer (181), and wherein the second conductive layer (181) comprises a metal or an alloy (paragraph 118). (Claim 19) Miyairi teaches wherein the semiconductor layer (130) is in contact with a top surface of the second electrode (140), wherein the semiconductor layer (130) comprises a metal oxide (paragraphs 74, 134), and wherein the second electrode (150) comprises a metal oxide (paragraph 130) having a composition different from that of the semiconductor layer. Allowable Subject Matter Claims 7, 14 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. (Claims 7, 14, 18) wherein a thickness of the second portion is smaller than a thickness of the first portion and a thickness of the third portion. Conclusion Prior art made of record and not relied upon, considered pertinent to applicant's disclosure are listed in PTO – 892 Form. Any inquiry concerning this communication or earlier communications from the examiner should be directed to IGWE U ANYA whose telephone number is (571)272-1887. The examiner can normally be reached 8:00 AM - 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272- 1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /IGWE U ANYA/Primary Examiner, Art Unit 2891 October 2, 2026
Read full office action

Prosecution Timeline

Sep 30, 2024
Application Filed
Oct 06, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
81%
With Interview (-3.8%)
2y 6m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 964 resolved cases by this examiner. Grant probability derived from career allowance rate.

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