DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on May 14, 2026 and September 30, 2024 have been considered by the Examiner.
Claim Objections
3. Claim 11 is objected to because of the following informalities:
a) Claim 11 line 1, change the dependency from “1” to --11--. To provide the proper antecedent basis for “the second insulating layer”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 8, 10, 14-17, 19 and 20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Sumitomo (JP 2013-033949; cited in the IDS).
Regarding claim 1, Sumitomo discloses a circuit board (100; see figure 1) comprising: a first insulating layer (22); and a circuit layer (10; see figure 1) disposed on the first insulating layer (22), wherein the circuit layer (10; see figure 1) includes: a first layer (10) disposed on the first insulating layer (22), and a second layer (12) partially disposed on a surface of the first layer (10), wherein a profile of the surface (paragraph 0058; surface is roughened or uneven) of the first layer (10) is different from a profile of a surface of the second layer (12; paragraph 0066, tin surface).
Regarding claim 2, Sumitomo discloses the circuit board (100), wherein the first layer (10) of the circuit layer includes: a first metal layer (10; paragraph 0055; Fe) disposed on an upper surface of the first insulating layer (22), and a second metal layer (10; paragraph 0055; Ni or other metal material such as Cu or Al) disposed on an upper surface of the first metal layer (paragraph 0055), wherein the second layer of the circuit layer includes a third metal layer (12; paragraph 0056; tin) disposed on an upper surface of the second metal layer (see figure 3), and wherein a profile of the upper surface of the second metal layer is different from a profile of an upper surface of the third metal layer (paragraph 0058; surface is roughened or uneven).
Regarding claim 3, Sumitomo discloses the circuit board (100), wherein the upper surface of the second metal layer (paragraph 0055 and 0058) includes a plurality of mountains and a plurality of valleys (paragraph 0058; surface is roughened or uneven), and wherein the third metal layer (10) is formed on the upper surface of the second metal layer to fill at least a portion of the plurality of valleys (paragraph 0055 and 0058).
Regarding claim 4, Sumitomo discloses the circuit board (100), wherein the third metal layer (12) is disposed on a side surface of the first metal layer (10; paragraph 0055) and a side surface of the second metal layer (10; paragraph 0055), and wherein each profile of the side surface of the first metal layer (10) and the side surface of the second metal layer (10) is different from a profile of a side surface of the third metal layer (12; paragraph 0058; surface is roughened or uneven; see figure 1).
Regarding claim 5, Sumitomo discloses the circuit board (100), wherein each of the side surface of the first metal layer (10) and the side surface of the second metal layer (10) includes a plurality of mountains and a plurality of valleys (paragraph 0058; surface is roughened or uneven); and wherein the third metal layer (12) fills at least a portion of the plurality of valleys of each of the side surfaces of the first and second metal layers (paragraph 0058).
Regarding claim 6, Sumitomo discloses the circuit board (100), wherein an upper surface of the circuit layer (10) includes: a first portion (see figure 1) corresponding to an upper surface of the first layer (10), and a second portion corresponding to an upper surface of the second layer (12).
Regarding claim 8, Sumitomo discloses the circuit board (100), wherein a side surface of the circuit layer (10,12) includes: a first portion corresponding to a side surface of the first layer (10), and a second portion corresponding to a side surface of the second layer (12; see figure 1).
Regarding claim 10, Sumitomo discloses the circuit board (100), further comprising: a second insulating layer (20) disposed on the first insulating layer (22) to cover the circuit layer (10,12), wherein a lower surface of the second insulating layer (20) includes: a first lower surface in contact with the first layer of the circuit layer (10), a second lower surface in contact with the second layer (12) of the circuit layer, and a third lower surface in contact with the first insulating layer (22; see figure 1).
Regarding claim 14, Sumitomo discloses the circuit board (100), wherein the first layer of the circuit layer (10) includes a first metal material (paragraph 0055; FeNi), and wherein the second layer (12; paragraph 0056, Tin) of the circuit layer includes a second metal material different from the first metal material.
Regarding claim 15, Sumitomo discloses the circuit board (100), wherein the first metal material (10) contains copper (paragraph 0055), and the second metal material (12) contains tin (paragraph 0056).
Regarding claim 16, Sumitomo discloses the circuit board (100), wherein the first metal layer (10) includes a first-first metal layer (paragraph 0055; Fe) and a first-second metal layer (10; paragraph 0055; Ni or other metal material such as Cu or Al ) disposed on the first-first metal layer, and wherein the second metal layer (12) is disposed on the first-second metal layer (paragraph 0055-0056).
Regarding claim 17, Sumitomo discloses a circuit board (100) comprising: a first insulating layer (22); a second insulating layer (20) disposed on the first insulating layer (22); and a circuit layer (10) disposed between the first insulating layer (22) and the second insulating layer (20), wherein an upper surface of the circuit layer (10) includes: a first upper surface including a first metallic material (paragraph 0055; FeNi), and a second upper surface including a second metal material (paragraph 0056; Tin) different from the first metal material (paragraph 0055), and wherein the second insulating layer (20) includes a contact portion in contact with the first upper surface and the second upper surface (see figure 1).
Regarding claim 19, Sumitomo discloses the circuit board (100), wherein the first metal (10; paragraph 0055) material includes copper (paragraph 0055; Cu), and wherein the second metallic material contains tin (12; paragraph 0056).
Regarding claim 20, Sumitomo discloses the circuit board (100), wherein a side surface of the circuit layer (10) includes a first side surface including the first metal material and a second side surface including the second metal material (paragraph 0055-0056; see figure 1), and wherein the first side surface and the second side surface are in contact with the second insulating layer (20).
5. Claims 1, 6-13, 17 and 18 are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by Adachi et al (US 2022/0077046; hereinafter Adachi; cited in the IDS)
Regarding claim 1, Adachi discloses a circuit board (100; see figure 1) comprising: a first insulating layer (21); and a circuit layer (11; see figure 1) disposed on the first insulating layer (21), wherein the circuit layer (11; see figure 3) includes: a first layer (1a) disposed on the first insulating layer (21; see figure 3), and a second layer (5) partially disposed on a surface of the first layer (1a; see figure 3), wherein a profile of the surface of the first layer (1a) is different from a profile of a surface of the second layer (5; see figure 3; paragraph 0046).
Regarding claim 6, Adachi discloses the circuit board (100), wherein an upper surface of the circuit layer (11) includes: a first portion (see figure 3) corresponding to an upper surface of the first layer (1a), and a second portion corresponding to an upper surface of the second layer (5).
Regarding claim 7, Adachi discloses the circuit board (100), wherein an arithmetic average roughness Ra of the upper surface of the circuit layer (11) has a range of 0.05 µm to 0.2µm (paragraph 0056), and wherein a ten-point average roughness Rz of the upper surface of the circuit layer is in a range of 0.1 pm to 1.0 µm (paragraph 0056).
Regarding claim 8, Adachi discloses the circuit board (100), wherein a side surface of the circuit layer (11) includes: a first portion corresponding to a side surface of the first layer (1a), and a second portion corresponding to a side surface of the second layer (see figure 3).
Regarding claim 9, Adachi discloses the circuit board (100), wherein an arithmetic average roughness Ra of the upper surface of the circuit layer (11) has a range of 0.05 µm to 0.2µm (paragraph 0056), and wherein a ten-point average roughness Rz of the upper surface of the circuit layer is in a range of 0.1 pm to 1.0 µm (paragraph 0056).
Regarding claim 10, Adachi discloses the circuit board (100), further comprising: a second insulating layer (22) disposed on the first insulating layer (21) to cover the circuit layer (11), wherein a lower surface of the second insulating layer (22) includes: a first lower surface in contact with the first layer (1a) of the circuit layer (11), a second lower surface in contact with the second layer (5) of the circuit layer (11), and a third lower surface in contact with the first insulating layer (21; see figure 3).
Regarding claim 11, Adachi discloses the circuit board (100), further comprising: a through electrode passing (4) through an upper surface of the second insulating layer (22) and a lower surface of the second insulating layer (22), wherein the through electrode (4) has an inclination that a width decreases toward the first insulating layer (21), and wherein a lower surface of the through electrode (4) includes: a first lower surface in contact with the first layer (1a) of the circuit layer (11), and a second lower surface in contact with the second layer (5) of the circuit layer (11; see figure 3).
Regarding claim 12, Adachi discloses the circuit board (100), wherein the first layer (1a) of the circuit layer (11) includes a concave portion concave toward the first insulating layer (21), and wherein the second layer (5) of the circuit layer (11) is disposed within the concave portion (see figure 3; paragraph 0046).
Regarding claim 13, Adachi discloses the circuit board (100), wherein the second layer (5) of the circuit layer (11) partially fills the concave portion (see figure 3; paragraph 0046).
Regarding claim 17, Adachi discloses a circuit board (100) comprising: a first insulating layer (21); a second insulating layer (22) disposed on the first insulating layer (21); and a circuit layer (11) disposed between the first insulating layer (21) and the second insulating layer (22), wherein an upper surface of the circuit layer (11) includes: a first upper surface including a first metallic material (1a; paragraph 0034), and a second upper surface including a second metal material (5; paragraph 0043; “a triazole compound” can be a metallic triazole compound. Furthermore, paragraph 0043 states: “The material of the coating film 5 is not limited to a silane coupling agent as long as the material can increase the adhesion strength between the first conductor layer 11 and the second insulating layer 22 as compared to the case where the second insulating layer 22 is directly formed on the first conductor layer 11; it is well known in the art that metal layers are frequently used to increase adhesion between two materials) different from the first metal material (paragraph 0043), and wherein the second insulating layer (22) includes a contact portion in contact with the first upper surface and the second upper surface (see figure 3).
Regarding claim 18, Adachi discloses the circuit board (100), further comprising: a through electrode passing (4) through an upper surface of the second insulating layer (22) and a lower surface of the second insulating layer (22), wherein the through electrode (4) has an inclination that a width decreases toward the first insulating layer (21), and wherein the through electrode (4) includes a contact portion in contact with the first upper surface and the second upper surface (see figure 3).
Conclusion
6. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ko et al (US 9,578,740), Kagohashi (US 12,652,755), Ha et al (US 9,161,460), Jeon et al (US 8,756,804), Kawamura et al (US 8,017,875), Inagaki et al (US 7,855,894), En et al (US 7,535,095), En (US 7,446,263) and Asai et al (US 6,376,052) disclose a circuit board.
7. Any inquiry concerning this communication should be directed to Angel R. Estrada at telephone number (571) 272-1973. The Examiner can normally be reached on Monday-Friday (8:30am -5:00pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Imani N. Hayman can be reached on (571) 270-5528. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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June 5, 2026
/ANGEL R ESTRADA/Primary Examiner, Art Unit 2841
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