Prosecution Insights
Last updated: October 23, 2026
Application No. 18/853,322

Capacitive Charge Storage and Transport Device for Room Temperature applications

Non-Final OA §112
Filed
Oct 01, 2024
Priority
Apr 11, 2022 — provisional 63/329,822 +1 more
Examiner
PATEL, REEMA
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
The Board of Trustees of the Leland Stanford Junior University
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
1015 granted / 1143 resolved
+20.8% vs TC avg
Moderate +6% lift
Without
With
+6.5%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
24 currently pending
Career history
1176
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
43.3%
+3.3% vs TC avg
§102
25.0%
-15.0% vs TC avg
§112
21.0%
-19.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1143 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statements (IDS) were submitted on 10/1/24 and 4/10/26. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements have been considered by the examiner. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 2-4 and 8-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 2 refers to a “classical capacitance of the semiconductor device”. It is unclear what is meant by this phrase because there does not appear to be a universal definition of what is considered “classical capacitance”. Claim 3 refers to a “classical capacitance of the semiconductor device”. It is unclear what is meant by this phrase because there does not appear to be a universal definition of what is considered “classical capacitance”. Claim 4 refers to a “classical capacitance of the semiconductor device”. It is unclear what is meant by this phrase because there does not appear to be a universal definition of what is considered “classical capacitance”. Claim 8 refers to a “a nonclassical behavior”. It is unclear what is meant by this phrase because there does not appear to be a universal definition of what is considered “nonclassical behavior”. Claim 9 refers to a “a nonclassical behavior”. It is unclear what is meant by this phrase because there does not appear to be a universal definition of what is considered “nonclassical behavior”. Allowable Subject Matter Claims 1, 5-7, and 10-11 are allowed. Claim 1 contains allowable subject matter because of the limitation the electrical bias includes an out-of-plane component perpendicular to the plane of the low-dimensional electron gas; wherein the room temperature MIS structure has topological states that are formed by application of the electrical bias followed by injection of charge carriers. Claims 5-7 and 10-11 depend on claim 1. The closest prior art is Zhang et al. (U.S. 2012/0138887 A1; “Zhang”) which discloses forming a low-dimensional electron gas in a room temperature MIS (Metal/Insulator/Semiconductor) structure with an electrical bias, wherein the electrical bias includes an in-plane component in a plane of the low-dimensional electron gas ([0093], [0108], [0113], [0079]). Yet, Zhang does not disclose the electrical bias includes an out-of-plane component perpendicular to the plane of the low-dimensional electron gas and wherein the room temperature MIS structure has topological states that are formed by application of the electrical bias followed by injection of charge carriers and these features are not rendered obvious by the prior art. Any inquiry concerning this communication or earlier communications from the examiner should be directed to REEMA PATEL whose telephone number is (571)270-1436. The examiner can normally be reached M-F, 8am-5pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /REEMA PATEL/Primary Examiner, Art Unit 2812 9/24/2026
Read full office action

Prosecution Timeline

Oct 01, 2024
Application Filed
Oct 01, 2024
Response after Non-Final Action
Jun 18, 2025
Response after Non-Final Action
Sep 29, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12772497
COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) APPARATUS WITH SELF-ALIGNED BACKSIDE CONTACT
4y 1m to grant Granted Oct 20, 2026
Patent 12772620
LIGHT EMITTING DIODE
2y 10m to grant Granted Oct 20, 2026
Patent 12765152
ELECTRON TRANSPORT LAYER FOR PEROVSKITE SOLAR CELL AND PEROVSKITE SOLAR CELL INCLUDING SAME
2y 9m to grant Granted Oct 13, 2026
Patent 12765053
THREE DIMENSIONAL INTEGRATED CIRCUIT AND FABRICATION THEREOF
3y 1m to grant Granted Oct 13, 2026
Patent 12765045
SEMICONDUCTOR DEVICE
3y 1m to grant Granted Oct 13, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
95%
With Interview (+6.5%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1143 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month