DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a FINAL OFFICE ACTION in response to the Amendment/ Remarks filed 06/02/2026. Claim 1-22 have been cancelled. Claims 23-42 are pending in the Application, of which Claims 23, 33 and 39 are independent.
Continuity/ Priority Information
The present Application 18853475 filed 10/02/2024 is a National Stage entry of PCT/CN2022/094857, International Filing Date: 05/25/2022.
Specification
The disclosure is objected to because of the following informalities:
Amend the following, Para. [0065], line 2, a baseboard management controller (BMC). Appropriate correction is required.
Response to Arguments
Applicant's arguments, see Amendment/ Remarks filed 06/02/2026, with respect to the rejection of Claims 23-42 under 35 U.S.C. 102(a)(1) as being anticipated by Tallam et al. (Pub. No. US 20170091013), have been fully considered but they are not persuasive, as set forth in the present office action.
With respect to the "baseboard management controller (BMC)" limitation, Applicant argues that the BMC of a computer system is a specialized, independent microcontroller embedded on a motherboard, whereas a PCIe root complex represents a central traffic controller of a computer's PCIe system. The root complex acts as a data-routing "highway" that connects the CPU to high-speed devices, while the BMC is a completely separate, independent microcontroller that monitors and manages the computer's hardware.
In response to Applicant arguments, the Examiner notes that the PCIe root complex as disclosed by Tallam is functionally equivalent to the BMC limitation, because they both perform the same function, of error monitoring/ reporting. For example, Tallam discloses para. [0022] The root complex 110 may also record and report errors detected in the connections and/or devices of the PCIe system 100. For example, with reference to FIG. 1A, when an error is detected in endpoint device 130, the endpoint device 130 may send an error message 101 to the root port in its hierarchy (e.g., RP2). The error message 101 may include a requester ID and a description of the error. For example, the requester ID may include information identifying endpoint device 130 as the originator of the error message 101.
With respect to the "disable correctable error reporting” limitation, Applicant argues that Tallam does not show contemplation for disabling correctable error reporting at the individual device level, but rather at a root port-level.
In response to Applicant arguments, Tallam discloses FIG. 4. [0053] The interrupt counter (Count.sub.INT) is compared with a reporting threshold (R_Threshold) to determine whether an error reporting limit has been reached and/or exceed for the corresponding root port (440). If the count value 203 exceeds the reporting threshold (as tested at 440), the root complex 200 may disable interrupt signaling for the corresponding root port (445). As best understood, the device referring to by Applicant as device 112, in Fig. 1, is the same as the device 130 in Tallam. Clearly, Tallam discloses disabling correctable error reporting at the individual device.
With respect to the "threshold-based error rate monitoring" limitation, Applicant argues that Tallam does not teach causing a BMC to perform the recited "threshold-based error rate monitoring."
In response to Applicant arguments, Tallam discloses [0022] The root complex 110 may also record and report errors detected in the connections and/or devices of the PCIe system 100. For example, with reference to FIG. 1A, when an error is detected in endpoint device 130, the endpoint device 130 may send an error message 101 to the root port in its hierarchy (e.g., RP2). The error message 101 may include a requester ID and a description of the error.
With respect to the "keeping track" limitation, Applicant argues that Tallam does not suggest "periodic error monitoring" during which tracking of when a correctable error has been logged by a particular device.
In response to Applicant arguments, Tallam discloses para. [0032] As described above, the error message 201 may include a requester ID and a description of the error. Upon receiving an error message 201, the interrupt module 220 may store the error message 201 in a corresponding partition of the error register 250 associated with the root port at which the error message 201 was received. For example, if the error message 201 is received via root port RP2, the interrupt module 220 may store the error message 201 in the “RP2” partition of the error register 250.
With respect to the "distinguishing between persistent and temporal errors" limitation, Applicant argues that there is no indication that Tallam's correctable errors corresponds to the recited "temporal errors" or that "uncorrectable errors" correspond to the recited "persistent errors." In the above-captioned patent application, the terms "temporal" and "persistent" are used in accordance with their ordinary and customary meaning, in which a temporal error is transient in nature in which the duration is temporary versus a persistent error, which is permanent.
In response to Applicant arguments, for the purpose of advancing prosecution of the Application, the terms are interpreted as described in the office action, i.e., “temporal error" corresponding to “correctable error” and “persistent error” corresponding to “uncorrectable error”.
For example, Tallam discloses para. [0050] the error message 201 may include a requester ID (e.g., identifying the error-reporting device) and/or a description of the error (e.g., whether the error is a correctable or uncorrectable error type). In some aspects, the interrupt module 220 may store the error message 201 in a corresponding partition (e.g., "RP2, " "RP3," or "RP4") of the error register 250 associated with the root port at which the error message 201 was received.
In response to Applicant arguments, regarding Claims 33, 39 and 24 with respect to the decrementing an error counter in accordance with a leak rate of a leaky bucket, Tallam discloses FIG. 2. [0034] The interrupt throwing module 230 receives the BER 202 and updates an interrupt count value 203 stored in the interrupt counter 260. More specifically, the interrupt throwing module 230 may update the count value 203 associated with the root port identified by the BER 202. For example, upon receiving the BER 202 identifying root port RP2, the interrupt throwing module 230 may increment the count value 203 stored in the “RP2” partition of the interrupt counter 260.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 23-42 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tallam et al. (Pub. No. US 20170091013) Pub. Date: 2017-03-30.
Regarding independent Claims 23, 33 and 39,Tallam discloses a system and method for error reporting in PCIe systems, comprising:
a baseboard management controller (BMC) coupled to the one or more processors; [0020] FIGS. 1A and 1B. The PCIe system 100 includes a root complex 110 corresponding to “baseband management controller”, a central processing unit (CPU) 120 corresponding to “processor”, a first endpoint device 130, a second endpoint device 140, and a switch 150. The CPU 120 is coupled to a first root port RP1 of the root complex 110. [0021] The root complex 110 provides a logical point-to-point connection (e.g., “interconnect” or “link”) between devices coupled to its respective root ports RP1-RP4. For example, a PCIe link between root ports RP1 and RP2 may enable the CPU 120 to communicate with endpoint device 130 (e.g., as a “requester” or “completer” of a PCIe transaction).
after a burst of correctable errors reported by a device exceeding an error threshold, disable correctable error reporting for the device, FIG. 4. [0053] The interrupt counter (Count.sub.INT) is compared with a reporting threshold (R_Threshold) to determine whether an error reporting limit has been reached and/or exceed for the corresponding root port (440). If the count value 203 exceeds the reporting threshold (as tested at 440), the root complex 200 may disable interrupt signaling for the corresponding root port (445). For example, while interrupt signaling is disabled for a given root port, the interrupt throwing module 230 may throttle or ignore any BERs received for that root port (e.g., by preventing the signaling of interrupts 204 in response to the received BERs).
during periodic error monitoring keeping track of when a correctable error has been logged by the device; FIG. 2. [0032] The interrupt module 220 may receive error messages (EM) 201 via one or more of the root ports RP2-RP4 of the device interface 210. As described above, the error message 201 may include a requester ID and a description of the error. Upon receiving an error message 201, the interrupt module 220 may store the error message 201 in a corresponding partition of the error register 250 associated with the root port at which the error message 201 was received.
distinguishing between persistent and temporal errors associated with the device based on the correctable errors. [0050] As described above, the error message 201 may include a requester ID (e.g., identifying the error-reporting device) and/or a description of the error (e.g., whether the error is a correctable corresponding to “temporal error” or uncorrectable error corresponding to “persistent error”. In some aspects, the interrupt module 220 may store the error message 201 in a corresponding partition (e.g., “RP2,” “RP3,” or “RP4”) of the error register 250 associated with the root port at which the error message 201 was received.
Regarding independent Claims 33 and 39 and dependent Claim 24, Tallam additionally discloses decrementing an error counter in accordance with a leak rate of a leaky bucket implemented by the management controller (BMC) for the device; and incrementing the error counter when a new correctable error has been logged by the device; FIG. 2. [0034] The interrupt throwing module 230 receives the BER 202 and updates an interrupt count value 203 stored in the interrupt counter 260. More specifically, the interrupt throwing module 230 may update the count value 203 associated with the root port identified by the BER 202. For example, upon receiving the BER 202 identifying root port RP2, the interrupt throwing module 230 may increment the count value 203 stored in the “RP2” partition of the interrupt counter 260.
Regarding Claims 25, 26, 34, 35, Tallam discloses wherein after the error counter exceeds a persistent error threshold, identify existence of a persistent error, wherein the persistent error is predictive of an imminent uncorrectable error associated with the device; [0056] If the CE value 205 does not exceed the correctable error threshold (as tested at 470), or if the received BER 202 indicates an uncorrectable error “persistent error” (as tested at 450), the root complex 200 may store the BER 202 in a circular buffer (480) and signal an interrupt to a CPU (490). For example, the interrupt throwing module 230 may add the BER 202 to the back of a BER queue stored in the circular buffer 270. The interrupt throwing module 230 may further signal an interrupt 204 to the CPU. In response to the interrupt 204, the CPU may send a worker thread 212 to the root complex 200 to process (and clear) each BER 202 stored in the circular buffer 270.
Regarding Claims 27, 36, 40, Tallam discloses wherein after the error counter falls to zero: identify the burst of correctable errors as the temporal error; and re-enable correctable error reporting for the device. [0038] Upon clearing all error messages for a particular root port, the worker thread 212 may generate a reset signal 205. The reset signal 205 may identify the particular root port partition of the error register 250 that was recently cleared. The interrupt throttling module 230 receives the reset signal 205 and re-enables interrupt signaling for the corresponding root port (e.g., by unmasking the error register 250 for RP2).
Regarding Claims 28, 37, 41, Tallam discloses wherein correctable errors of the burst of correctable errors are individually reported to a system management interrupt (SMI) handler of a basic input/output system (BIOS) running on the one or more processors. [0051] The root complex 200 generates a basic error report (BER) for the error-detecting root port (420). For example, the interrupt module 220 may generate the BER 202 based on the received error message 201. In some aspects, the BER 202 may contain minimal information about the reported error. For example, the BER 202 may identify the root port (e.g., root port RP2, RP3, or RP4) that received the error message 201 and/or the type of error (e.g., correctable or uncorrectable) indicated by the error message 201. If the count value 203 exceeds the reporting threshold (as tested at 440), the root complex 200 may disable interrupt signaling for the corresponding root port (445).
Regarding Claims 29, 30, 38, 42, Tallam discloses correctable errors reported by the device to a desired notification rate, based on a configurable error monitoring interval that controls the periodic error monitoring. [0048] The root complex 110 selectively performs an interrupt routine based at least in part on the interrupt count for the given root port (330). For example, the interrupt throttling module 112 may compare the interrupt count for the given root port with a reporting threshold for that root port to determine whether an error reporting limit has been reached. If the interrupt count exceeds (or has reached) the reporting threshold, the interrupt throwing module 112 may disable interrupt signaling for the corresponding root port.
Regarding Claims 31, 32, Tallam discloses wherein the device comprises an integrated graphics processing unit (GPU). [0020] FIGS. 1A and 1B show a PCIe system 100a having a central processing unit (CPU) 120.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
(Pub. No. US 20210255939) Chaiken et al. see Abstract. An information handling system includes a non-volatile storage device communicatively coupled to a boot processor and an application processor. The application processor is configured to detect a catastrophic failure corresponding to claimed “persistent error” of the hang sensitive transaction. In response to the detection of the catastrophic failure, the application processor retrieves the information stored at the memory device and store the information at the non-volatile storage device.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: July 2, 2026
Final Rejection 20260702
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV
Prosecution Insights