Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in JAPAN on 05/24/2022. Applicant cannot rely upon the certified copy of the foreign priority application to overcome this rejection because a translation of said application has not been made of record in accordance with 37 CFR 1.55. When an English language translation of a non-English language foreign application is required, the translation must be that of the certified copy (of the foreign application as filed) submitted together with a statement that the translation of the certified copy is accurate. See MPEP §§ 215 and 216.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 10/03/2024 has/have been considered by the examiner and made of record in the application file.
Claim Interpretation
Claim 1 recites properties and/or functions of the various material layers including “a barrier layer . . . induces the carriers”, “a first spacer layer . . . decreases alloy scattering”, “a second spacer layer . . . traps the carriers”. Claims 2, 3, 6, 8,10, and 19 each recite details of the relative band gaps, energy potentials, or conduction bands of the layers. MPEP section 2112.02.I states that “Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established”. For the purposes of this examination, when the structure recited in a reference is substantially identical to the claims, any claimed properties and/or functions will be presumed to be inherent in the reference device absent any statement in the reference or showing the property not to be inherent.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 20 both recite “a barrier layer . . . that induces the carriers” which is unclear. It is not clear what is meant by “induces the carriers” and the specification does not provide any further explanation for what the verb “induces” is providing in this limitation. To induce means to give rise to as a possible definition but it is not clear how the barrier layer gives rise to the charge carriers. It would seem to the examiner that all components of a transistor work in unison to give rise to flowing charge carriers in the channel region. However, how the barrier layer specifically does so is not clearly defined. Therefore, claim(s) 1 and 20 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 2-19 is/are rejected at least for their dependencies. For the purposes of this examination, it will be interpreted that any layer in a HEMT may work to “induce carriers”.
Claims 12 and 13 are unclear in view of the specification and drawings. Claim 12 recites the limitation “the first spacer layer has an Al composition profile having a maximal value in a thickness direction and a Ga composition profile having a minimal value in the thickness direction” and claim 13 recites the limitation “the second spacer layer has an Al composition profile having a minimal value in the thickness direction and a Ga composition profile having a maximal value in the thickness direction” which are unclear. The claims do not specify if these maximal/minimal values are local to the individual layers or global for the entire thickness of the device. For example, any individual layer will necessarily individually have a local minimum composition of a given element somewhere in its thickness direction even if the structure is perfectly homogenous and the local minimum is also the local maximum for the layer, or even if the layer does not include the element and the local minimum is zero, such that it is unclear what this claim is describing. In the alternative, a claim to a global maximum or minimum value is unclear in view of the drawings, specifically Figure 2, which shows that the first spacer layer (#61) does not have “an Al composition profile having a maximal value in a thickness direction and a Ga composition profile having a minimal value in the thickness direction” if reference is being made as global since Al is higher in the barrier layer (#7) and Ga is lower in the barrier layer. In the same manner Figure 2 shows that the second spacer layer (#62) does not have “an Al composition profile having a minimal value in the thickness direction and a Ga composition profile having a maximal value in the thickness direction” if reference is being made as global since Al is lower in the channel layer (#5) and Ga is higher in the channel layer. Therefore, claim(s) 12 and 13 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 14-16 is/are rejected at least for their dependencies. For the purposes of this examination, it will be interpreted that applicant is referring to local maxima and or minima in the claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4, 5, and 17-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2023/0070031 A1; Chen et al.; 03/2023; (“031”).
Regarding Claim 1. Chen discloses A high electron mobility transistor (#100-2, Figure 5, HEMT) comprising:
a channel layer (#110, Figure 5, channel layer) through which carriers are to flow ([0027], carriers necessarily flow through 2DEG region #130 of the channel of a transistor);
a pair of respective main electrodes (#122/#124, Figure 5, source and drain electrodes) coupled to one end and another end of the channel layer (Figure 5, #122 and #124 are coupled to opposing ends of #110);
a barrier layer (#115, Figure 5, cap layer) that is disposed at the channel layer and induces the carriers (Figure 5, #115 is at the channel layer, which does not require contact, and is interpreted as capable of inducing the carriers, see 35 U.S.C. 112(b) rejection above, since a positive voltage may be generated on its surface by the gate electrode to attract electrons);
a gate electrode (#126, Figure 5) disposed at an intermediate part of the channel layer with the barrier layer interposed therebetween (Figure 5, #126 is disposed at an intermediate part of #110 and has #115 interposed therebetween);
a first spacer layer (#112, Figure 5, barrier layer) that is disposed between the channel layer and the barrier layer (Figure 5, #112 is disposed between #115 and #110) and decreases alloy scattering (Figure 5, #112 necessarily blocks alloy scattering from #115 by acting as a barrier to the movement of elements therebetween); and
a second spacer layer (#114, Figure 5, composition gradient layer) that is disposed between the first spacer layer and the barrier layer in a region overlapping the gate electrode (Figure 5, #114 is disposed between #112 and #115 in a region overlapping #126) and traps the carriers ([0029], #114 prevents the flow of current through surface leakage from the HEMT, i.e. it traps the charges).
Regarding Claim 4. Chen discloses The high electron mobility transistor according to claim 1, wherein the channel layer is a nitride semiconductor ([0027], #110 may be GaN).
Regarding Claim 5. Chen discloses The high electron mobility transistor according to claim 4, wherein the channel layer is GaN ([0027], #110 may be GaN).
Regarding Claim 17. Chen discloses The high electron mobility transistor according to claim 1, wherein the first spacer layer (#112) has a thickness larger than a thickness of the second spacer layer (#114) ([0044], #114 may be 10%-50% of the thickness of #112, i.e. #112 is thicker).
Regarding Claim 18. Chen discloses The high electron mobility transistor according to claim 17, wherein the thickness of the first spacer layer (#112) is equal to or more than 0.5 nm ([0044], #112 is thicker than #114 and #114 has a smallest thickness of 2 nm such that #112 is necessarily thicker than 0.5 nm).
Regarding Claim 19. Chen discloses The high electron mobility transistor according to claim 1, wherein, in a state where a positive bias is applied to the gate electrode, a conduction band of the second spacer layer (#114) is higher than a Fermi level and a conduction band of the channel layer (#110) ([0029], #114 is provided to stop the flow of electrons out of the channel and has a conduction band which is higher than the channel and the fermi level in order to stop that flow of electrons).
Regarding Claim 20. Chen discloses A semiconductor device comprising a high electron mobility transistor (#100-2, Figure 5, HEMT), wherein the high electron mobility transistor includes
a channel layer (#110, Figure 5, channel layer) through which carriers are to flow ([0027], carriers necessarily flow through 2DEG region #130 of the channel of a transistor);
a pair of respective main electrodes (#122/#124, Figure 5, source and drain electrodes) coupled to one end and another end of the channel layer (Figure 5, #122 and #124 are coupled to opposing ends of #110);
a barrier layer (#115, Figure 5, cap layer) that is disposed at the channel layer and induces the carriers (Figure 5, #115 is at the channel layer, which does not require contact, and is interpreted as capable of inducing the carriers, see 35 U.S.C. 112(b) rejection above, since a positive voltage may be generated on its surface by the gate electrode to attract electrons);
a gate electrode (#126, Figure 5) disposed at an intermediate part of the channel layer with the barrier layer interposed therebetween (Figure 5, #126 is disposed at an intermediate part of #110 and has #115 interposed therebetween);
a first spacer layer (#112, Figure 5, barrier layer) that is disposed between the channel layer and the barrier layer (Figure 5, #112 is disposed between #115 and #110) and decreases alloy scattering (Figure 5, #112 necessarily blocks alloy scattering from #115 by acting as a barrier to the movement of elements therebetween); and
a second spacer layer (#114, Figure 5, composition gradient layer) that is disposed between the first spacer layer and the barrier layer in a region overlapping the gate electrode (Figure 5, #114 is disposed between #112 and #115 in a region overlapping #126) and traps the carriers ([0029], #114 prevents the flow of current through surface leakage from the HEMT, i.e. it traps the charges).
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2024/0234564 A1; Tasai, Kunihiko; 07/2024; (“Tasai”).
Regarding Claim 1. Tasai discloses A high electron mobility transistor (#10B, Figure 10, semiconductor device which may be a HEMT according to [0045]) comprising:
a channel layer (#4, Figure 10, channel layer) through which carriers are to flow ([0045], carriers necessarily flow through 2DEG region #K45 of the channel of a transistor);
a pair of respective main electrodes (#S/#D, Figure 10, source and drain electrodes) coupled to one end and another end of the channel layer (Figure 10, #S and #D are indirectly coupled to opposing ends of #4);
a barrier layer (#7, Figure 10, barrier layer) that is disposed at the channel layer and induces the carriers (Figure 10, [0045], #7 is at the channel layer where at does not require direct contact and may be polarized to induce carrier);
a gate electrode (#G, Figure 10, gate electrode) disposed at an intermediate part of the channel layer with the barrier layer interposed therebetween (Figure 10, #G is disposed at an intermediate part of #4 with #7 therebetween);
a first spacer layer (#5, Figure 10, first spacer layer) that is disposed between the channel layer and the barrier layer (Figure 10, #5 is between #4 and #7) and decreases alloy scattering ([0052], #5 suppresses alloy scattering); and
a second spacer layer (#6, Figure 10, second spacer layer) that is disposed between the first spacer layer and the barrier layer in a region overlapping the gate electrode (Figure 10, #6 is between #5 and #7 in a region that overlaps #G) and traps the carriers ([0056], #6 has a lower band gap than #5 and #7 on either side such that it necessarily forms a quantum well to trap carriers).
Regarding Claim 2. Tasai discloses The high electron mobility transistor according to claim 1, wherein the second spacer layer has a band gap narrower than a band gap of the first spacer layer and a band gap of the barrier layer ([0056], #6 has a lower band gap than #5 and #7 on either side) and wider than a band gap of the channel layer (see claim interpretation, being made out of similar materials between the reference and claims/specification of the instant application , #6 ([0055], AlGaInN) is interpreted to have a narrower band gap than the channel ([0049], GaN)).
Regarding Claim 3. Tasai discloses The high electron mobility transistor according to claim 2, wherein the second spacer layer has concave energy potential formed to be curved toward a side of a Fermi level with respect to energy potential of the first spacer layer and energy potential of the barrier layer ([0056], #6 has a lower band gap than #5 and #7 on either side such that its energy potential is necessarily curved toward a side of the fermi level with respect to #5 and #7).
Regarding Claim 4. Tasai discloses The high electron mobility transistor according to claim 1, wherein the channel layer is a nitride semiconductor ([0049, #4 is GaN).
Regarding Claim 5. Tasai discloses The high electron mobility transistor according to claim 4, wherein the channel layer is GaN ([0049], #4 is GaN).
Regarding Claim 6. Tasai discloses The high electron mobility transistor according to claim 5, wherein the barrier layer (#7) is a nitride semiconductor ([0059], #7 may be AlInN) having a band gap wider than a band gap of the channel layer ([0050], #4 has a smaller band gap than #7).
Regarding Claim 7. Tasai discloses The high electron mobility transistor according to claim 6, wherein the barrier layer is Alx3In[1−x3]N, where 0<x3<1 is satisfied ([0059], barrier layer 7 may include an undoped u-Alx3In(1-x3)N).
Regarding Claim 8. Tasai discloses The high electron mobility transistor according to claim 7, wherein the first spacer layer is a nitride semiconductor ([0053], #5 may be AlInGaN) having a band gap wider than the band gap of the channel layer ([0050], #4 has a smaller band gap than #5).
Regarding Claim 9. Tasai discloses The high electron mobility transistor according to claim 8, wherein the first spacer layer is Alx1Iny1Ga[1−x1−y1]N, where 0<x1<1, 0≤y1<1, and 0<x1+y1<1 are satisfied ([0053], “first spacer layer 5 may include epitaxially-grown Alx1Iny1Ga(1-x1-y1)N (0<x1≤1, 0≤y1<1, 0≤x1+y1≤1)”).
Regarding Claim 10. Tasai discloses The high electron mobility transistor according to claim 9, wherein the second spacer layer is a nitride semiconductor ([0055], AlGaInN) having a band gap narrower than a band gap of the first spacer layer and a band gap of the barrier layer ([0056], #6 has a lower band gap than #5 and #7 on either side) and wider than the band gap of the channel layer (see claim interpretation, being made out of similar materials between the reference and claims/specification of the instant application , #6 ([0055], AlGaInN) is interpreted to have a narrower band gap than the channel ([0049], GaN)).
Regarding Claim 11. Tasai discloses The high electron mobility transistor according to claim 10, wherein the second spacer layer is Alx2Iny2Ga[1−x2−y2]N, where 0<x2<1, 0<y2<1, and 0<x2+y2<1 are satisfied ([0055], “second spacer layer 6 includes Alx2Iny2Ga(1-x2-y2)N (0<x2<x1≤1, 0≤y2<1, 0<x2+y2<1)”.
Regarding Claim 12. Tasai discloses The high electron mobility transistor according to claim 11, wherein the first spacer layer has an Al composition profile having a maximal value in a thickness direction and a Ga composition profile having a minimal value in the thickness direction (Figure 10, #5 necessarily has a local max Al and a local min Ga somewhere along its thickness direction, see 112(b) rejection above).
Regarding Claim 13. Tasai discloses The high electron mobility transistor according to claim 12, wherein the second spacer layer has an Al composition profile having a minimal value in the thickness direction and a Ga composition profile having a maximal value in the thickness direction (Figure 10, #6 necessarily has a local min Al and a local max Ga somewhere along its thickness direction, see 112(b) rejection above).
Regarding Claim 14. Tasai discloses The high electron mobility transistor according to claim 13, wherein
an Al composition ratio increases from the channel layer ([0049], GaN) to the first spacer layer ([0053], Alx1Iny1Ga[1−x1−y1]N) (i.e. Al necessarily increases in this direction since the channel has no Al while the first spacer does),
the Al composition ratio decreases from the first spacer layer to the second spacer layer ([0056], “a composition ratio of Al in the second spacer layer 6 is lower than the composition ratio of Al in both the first spacer layer 5 and the barrier layer 7”, i.e. Al decreases from #5 to #6), and
the Al composition ratio increases from the second spacer layer to the barrier layer ([0056], “a composition ratio of Al in the second spacer layer 6 is lower than the composition ratio of Al in both the first spacer layer 5 and the barrier layer 7”, i.e. Al increases from #6 to #7).
Regarding Claim 15. Tasai discloses The high electron mobility transistor according to claim 14, wherein
a Ga composition ratio decreases from the channel layer ([0049], GaN) to the first spacer layer ([0053], Alx1Iny1Ga[1−x1−y1]N) (i.e. Ga necessarily decreases in this direction since the channel has no Al or In to take the place of Ga),
the Ga composition ratio increases from the first spacer layer to the second spacer layer ([0056], “the second spacer layer 6 having a higher Ga concentration than the Ga concentration in the first spacer layer 5 and the Ga concentration in the barrier layer 7 ”, i.e. Ga increases from #5 to #6), and
the Ga composition ratio decreases from the second spacer layer to the barrier layer ([0056], “the second spacer layer 6 having a higher Ga concentration than the Ga concentration in the first spacer layer 5 and the Ga concentration in the barrier layer 7 ”, i.e. Ga decreases from #6 to #7).
Regarding Claim 16. Tasai discloses The high electron mobility transistor according to claim 15, wherein an In composition ratio increases from the second spacer layer ([0055], AlGaInN) to the barrier layer ([0059], #7 may be AlInN) (i.e. In necessarily decreases in this direction since the barrier has no Ga or to take the place of In and thus may have more In).
Regarding Claim 17. Tasai discloses The high electron mobility transistor according to claim 1, wherein the first spacer layer (#5) has a thickness larger than a thickness of the second spacer layer (6) ([0054] and [0057], #5 may have a thickness of up to 3 nm while #6 may have a thickness as low as 0.5 nm such that #5 is thicker).
Regarding Claim 18. Tasai discloses The high electron mobility transistor according to claim 17, wherein the thickness of the first spacer layer is equal to or more than 0.5 nm ([0054], #5 may have a thickness of 0.5-1.5 nm preferably).
Regarding Claim 19. Tasai discloses The high electron mobility transistor according to claim 1, wherein, in a state where a positive bias is applied to the gate electrode, a conduction band of the second spacer layer (#6) is higher than a Fermi level and a conduction band of the channel layer ([0057], #6 is provided to stop the flow of electrons out of the channel and has a conduction band which is higher than the channel and the fermi level in order to stop that flow of electrons, see claim interpretation for these elements as being made out of the same materials in the application and reference)
Regarding Claim 20. Tasai discloses A semiconductor device comprising a high electron mobility transistor (#10B, Figure 10, semiconductor device which may be a HEMT according to [0045]), wherein
the high mobility transistor includes
a channel layer (#4, Figure 10, channel layer) through which carriers are to flow ([0045], carriers necessarily flow through 2DEG region #K45 of the channel of a transistor);
a pair of respective main electrodes (#S/#D, Figure 10, source and drain electrodes) coupled to one end and another end of the channel layer (Figure 10, #S and #D are indirectly coupled to opposing ends of #4);
a barrier layer (#7, Figure 10, barrier layer) that is disposed at the channel layer and induces the carriers (Figure 10, [0045], #7 is at the channel layer where at does not require direct contact and may be polarized to induce carrier);
a gate electrode (#G, Figure 10, gate electrode) disposed at an intermediate part of the channel layer with the barrier layer interposed therebetween (Figure 10, #G is disposed at an intermediate part of #4 with #7 therebetween);
a first spacer layer (#5, Figure 10, first spacer layer) that is disposed between the channel layer and the barrier layer (Figure 10, #5 is between #4 and #7) and decreases alloy scattering ([0052], #5 suppresses alloy scattering); and
a second spacer layer (#6, Figure 10, second spacer layer) that is disposed between the first spacer layer and the barrier layer in a region overlapping the gate electrode (Figure 10, #6 is between #5 and #7 in a region that overlaps #G) and traps the carriers ([0056], #6 has a lower band gap than #5 and #7 on either side such that it necessarily forms a quantum well to trap carriers).
Claim(s) 1-16 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by US 2022/0189780 A1; Kostelnik et al.; 06/2022; (“Kostelnik”).
Regarding Claim 1. Kostelnik discloses A high electron mobility transistor (Figure 7, High electron mobility transistor according to [0010]) comprising:
a channel layer (#106, Figure 7) through which carriers are to flow (Figure 7, carriers necessarily flow through a transistor channel);
a pair of respective main electrodes (#722/#726, Figure 7, drain and source electrodes) coupled to one end and another end of the channel layer (Figure 7, #722 and #726 are coupled to opposing ends of #106);
a barrier layer ([0037], a “further layer” may be disposed on #1084 and is interpreted as a barrier layer) that is disposed at the channel layer and induces the carriers (Figure 7, the further layer on #1084 would be at the channel layer and may induce carriers as part of operation);
a gate electrode (#724, Figure 7, gate interconnect) disposed at an intermediate part of the channel layer with the barrier layer interposed therebetween (Figure 7, #724 is disposed at an intermediate part of #106 with the further layer on #1084 therebetween);
a first spacer layer (#1082, Figure 7, lower film) that is disposed between the channel layer and the barrier layer (Figure 7, #1082 is disposed between #106 and the layer on #1084) and decreases alloy scattering ([0036], based on similar materials to the application, it is interpreted that #1082 may decrease alloy scattering, see claim interpretation above); and
a second spacer layer (#1084, Figure 7, upper film) that is disposed between the first spacer layer and the barrier layer in a region overlapping the gate electrode (Figure 7, #1084 is disposed between #1082 and the layer above #1084 overlapping with #724) and traps the carriers ([0036]-[0037], the lower aluminum content of #1084 will result in a narrower bandgap and carrier trapping).
Regarding Claim 2. Kostelnik discloses The high electron mobility transistor according to claim 1, wherein the second spacer layer has a band gap narrower than a band gap of the first spacer layer and a band gap of the barrier layer ([0036]-[0037], the lower aluminum content of #1084 will result in a narrower bandgap compared to #1082 and the layer above #1084) and wider than a band gap of the channel layer ([0032], #106 may be GaN, [0036], #1084 may be AlGaN which has a wider bandgap).
Regarding Claim 3. Kostelnik discloses The high electron mobility transistor according to claim 2, wherein the second spacer layer has concave energy potential formed to be curved toward a side of a Fermi level with respect to energy potential of the first spacer layer and energy potential of the barrier layer ([0036]-[0037], the lower aluminum content of #1084 will result in a narrower bandgap compared to #1082 and the layer above #1084 which will cause a concave energy potential relative to #1082 and the layer above #1084 towards the fermi level).
Regarding Claim 4. Kostelnik discloses The high electron mobility transistor according to claim 1, wherein the channel layer is a nitride semiconductor ([0032], #106 may be GaN).
Regarding Claim 5. Kostelnik discloses The high electron mobility transistor according to claim 4, wherein the channel layer is GaN ([0032], #106 may be GaN).
Regarding Claim 6. Kostelnik discloses The high electron mobility transistor according to claim 5, wherein the barrier layer is a nitride semiconductor ([0037]) having a band gap wider than a band gap of the channel layer ([0037], based on the ratios provided the further layer above #1084 may be AlInN with a ratio having a higher bandgap than the GaN channel).
Regarding Claim 7. Kostelnik discloses The high electron mobility transistor according to claim 6, wherein the barrier layer is Alx3In[1−x3]N, where 0<x3<1 is ([0037], based on the ratios provided the further layer above #1084 layer may be AlInN with a ratio in the range provided).
Regarding Claim 8. Kostelnik discloses The high electron mobility transistor according to claim 7, wherein the first spacer layer is a nitride semiconductor ([0036], #1082 may be AlInGaN) having a band gap wider than the band gap of the channel layer ([0036], #1082 may have ratios which have a wider than a GaN channel).
Regarding Claim 9. Kostelnik discloses The high electron mobility transistor according to claim 8, wherein the first spacer layer is Alx1Iny1Ga[1−x1−y1]N, where 0<x1<1, 0≤y1<1, and 0<x1+y1<1 are satisfied ([0036], #1082 may be AlInGaN with the given ratio restrictions)
Regarding Claim 10. Kostelnik discloses The high electron mobility transistor according to claim 9, wherein the second spacer layer is a nitride semiconductor ([0036], #1084 may be AlInGaN) having a band gap narrower than a band gap of the first spacer layer and a band gap of the barrier layer ([0036]-[0037], the lower Al content will result in #1084 having a narrower bandgap) and wider than the band gap of the channel layer ([0032], #106 is GaN, [0036], #1084 may be AlGaInN with ratios which have a wider bandgap than the channel).
Regarding Claim 11. Kostelnik discloses The high electron mobility transistor according to claim 10, wherein the second spacer layer is Alx2Iny2Ga[1−x2−y2]N, where 0<x2<1, 0<y2<1, and 0<x2+y2<1 are satisfied ([0036], #1084 may be AlInGaN with the given ratio restrictions).
Regarding Claim 12. Kostelnik discloses The high electron mobility transistor according to claim 11, wherein the first spacer layer has an Al composition profile having a maximal value in a thickness direction and a Ga composition profile having a minimal value in the thickness direction ([0036], #1082 has a local maximum for Al due to the lower content in the #106 and #1084 while having a local minimum Ga content due to the higher Al content).
Regarding Claim 13. Kostelnik discloses The high electron mobility transistor according to claim 12, wherein the second spacer layer has an Al composition profile having a minimal value in the thickness direction and a Ga composition profile having a maximal value in the thickness direction ([0036]-[0037], #1084 has a local minimum for Al due to the higher content in #1082 and the layer above #1084 while having a local maximum Ga content due to the lower Al content).
Regarding Claim 14. Kostelnik discloses The high electron mobility transistor according to claim 13, wherein
an Al composition ratio increases from the channel layer to the first spacer layer ([0036]-[0037], #1082 has higher Al content than the GaN channel),
the Al composition ratio decreases from the first spacer layer to the second spacer layer ([0036]-[0037], #1084 has lower Al content than #1082), and
the Al composition ratio increases from the second spacer layer to the barrier layer ([0036]-[0037], #1084 has lower Al content than the further layer above #1084).
Regarding Claim 15. Kostelnik discloses The high electron mobility transistor according to claim 14, wherein
a Ga composition ratio decreases from the channel layer to the first spacer layer ([0036]-[0037], #1082 has lower Ga content than the GaN channel due to the presence of at least Al),
the Ga composition ratio increases from the first spacer layer to the second spacer layer ([0036]-[0037], #1084 has higher Ga content than #1082 due at least to the reduced Al), and
the Ga composition ratio decreases from the second spacer layer to the barrier layer ([0036]-[0037], #1084 has higher Ga content than the further layer above #1084 due to the increase Al in the further layer).
Regarding Claim 16. Kostelnik discloses The high electron mobility transistor according to claim 15, wherein an In composition ratio increases from the second spacer layer to the barrier layer ([0036]-[0037], based on the ratios provided, the In content may increase from #1084 to the layer above #1084).
Regarding Claim 19. Kostelnik discloses The high electron mobility transistor according to claim 1, wherein, in a state where a positive bias is applied to the gate electrode, a conduction band of the second spacer layer is higher than a Fermi level and a conduction band of the channel layer ([0036], the purpose of #1084 is to function as a barrier layer such that when a positive voltage is applied charges do not flow through it to the gate, i.e. the conduction band must remain higher than the Fermi level and the conduction band of the channel when a positive bias is applied, particularly in the case of a low positive bias since #1084 has a wider bandgap than #106 as described above)
Regarding Claim 20. Kostelnik discloses A semiconductor device comprising a high electron mobility transistor (Figure 7, High electron mobility transistor according to [0010]) wherein
the high mobility transistor includes
a channel layer (#106, Figure 7) through which carriers are to flow (Figure 7, carriers necessarily flow through a transistor channel);
a pair of respective main electrodes (#722/#726, Figure 7, drain and source electrodes) coupled to one end and another end of the channel layer (Figure 7, #722 and #726 are coupled to opposing ends of #106);
a barrier layer ([0037], a “further layer” may be disposed on #1084 and is interpreted as a barrier layer) that is disposed at the channel layer and induces the carriers (Figure 7, the further layer on #1084 would be at the channel layer and may induce carriers as part of operation);
a gate electrode (#724, Figure 7, gate interconnect) disposed at an intermediate part of the channel layer with the barrier layer interposed therebetween (Figure 7, #724 is disposed at an intermediate part of #106 with the further layer on #1084 therebetween);
a first spacer layer (#1082, Figure 7, lower film) that is disposed between the channel layer and the barrier layer (Figure 7, #1082 is disposed between #106 and the layer on #1084) and decreases alloy scattering ([0036], based on similar materials to the application, it is interpreted that #1082 may decrease alloy scattering, see claim interpretation above); and
a second spacer layer (#1084, Figure 7, upper film) that is disposed between the first spacer layer and the barrier layer in a region overlapping the gate electrode (Figure 7, #1084 is disposed between #1082 and the layer above #1084 overlapping with #724) and traps the carriers ([0036]-[0037], the lower aluminum content of #1084 will result in a narrower bandgap and carrier trapping).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0189780 A1; Kostelnik et al.; 06/2022; (“Kostelnik”).
Regarding Claim 17. Kostelnik discloses The high electron mobility transistor according to claim 1.
Kostelnik does not explicitly disclose that the first spacer layer (#1082) has a thickness larger than a thickness of the second spacer layer (#1084).
However, Kostelnik does teach that “the lower film 1082 may have a thickness in a range from 5 nm to 8 nm, and the upper film 1084 may have a thickness in a range from 5 nm to 15 nm” in [0036] which encompasses values where #1082 is thicker than #1084. Furthermore, Kostelnik does not require #1082 to be thinner than #1084 and further states in [0036] that “Other compositions and thicknesses may be used without deviating from the concepts as described herein”.
It is therefore interpreted by the examiner that it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the first spacer layer to be thicker than the second spacer layer in Kostelnik based on the options provided. This is interpreted by the examiner as obvious change in size/proportion (see MPEP 2144.04.IV.A) given Kostelnik’s statement that “Other compositions and thicknesses may be used without deviating from the concepts as described herein” such that a device having the claimed relative dimensions would not perform differently than the prior art device.
Regarding Claim 18. Kostelnik discloses The high electron mobility transistor according to claim 17, wherein the thickness of the first spacer layer is equal to or more than 0.5 nm ([0036], #1082 may have a thickness of 5-8 nm).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 10,797,168 B1; Moens et al; 10/2020 – Figures 6 and 7 disclose a HEMT having a three layer structure (#1082, #1084, and #1086) between the channel layer (#106) and the gate electrode (#224) wherein the middle layer of the three layer structure includes a smaller bandgap than the other two layers in order to trap charge carriers (see abstract) for recombination.
GaN-Based Submicrometer HEMTs With Lattice-Matched InAlGaN Barrier Grown by MBE; Lim et al.; 07/2010 – Figure 1 discloses a HEMT having a multilayer structure between a GaN channel layer and a gate electrode, the multilayer structure including AlN and InAlGaN.
Design and Simulation of High Performance Lattice Matched Double Barrier Normally Off AlInGaN/GaN HEMTs; Shrestha et al.; 08/2020 – Figure 1 discloses a HEMT having a multilayer structure between a GaN channel layer and a gate electrode, the multilayer structure including InAlGaN at different compositions to form a charge trap (see Device Structure and Methodology section).
Optimization of Graded AlInN/AlN/GaN HEMT Device Performance Based on Quaternary Back Barrier for High Power Application; Rahman et al.; 11/2017 – Figure 1b discloses a HEMT having a multilayer structure between a InGaN channel layer and a gate electrode, the multilayer structure including InAlGaN at different compositions.
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/TYLER J WIEGAND/Examiner, Art Unit 2812
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