DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-7 and 10-14 have been amended.
Claims 8 and 9 have been cancelled.
Claim 15 has been added.
Claims 1-7 and 10-15 have been examined.
The specification, drawing, and claim objections in the previous Office Action have been addressed and are withdrawn, except as otherwise indicated below.
The § 112 rejections in the previous Office Action have been addressed and are withdrawn.
Drawings
The drawings are objected to because of the following informalities.
The format of the view numbers is improper. Please amend from “Figure” to FIG.” to comply with 37 CFR 1.84(u), which states, “View numbers must be preceded by the abbreviation "FIG."”.
Figures 5 and 8 include text that is improperly oriented, e.g., “end” and “PE control unit.” The figures therefore fail to comply with 37 CFR 1.84(i), which states, “Words must appear in a horizontal, left-to-right fashion when the page is either upright or turned so that the top becomes the right side, except for graphs utilizing standard scientific convention to denote the axis of abscissas (of X) and the axis of ordinates (of Y).”
The figures do not show the elements recited in newly added claim 15. The figures therefore fail to comply with 37 CFR 1.83(a), which states, “The drawing in a nonprovisional application must show every feature of the invention specified in the claims.”
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Appropriate correction is required. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 15 is objected to because of the following informalities.
Claim 15 recites, at line 4, “fibric tile.” This appears to be a typographical error. Applicant may have intended “ fabric tile.”
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 and 10-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 recites, at lines 6-7 and 8-9, “the at least one storage elements.” There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this limitation is interpreted as, “the one or more storage elements.”
Claim 1 recites, at line 7, “the arithmetic logic unit.” There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this limitation is interpreted as, “each of the at least one arithmetic logic units.”
Claim 1 recites, at line 12, “supports a plurality of target instruction pointers.” It cannot be determined what is encompassed by the term “supports.” The term is vague and ambiguous and renders the scope of the claims indefinite. For purposes of examination, this limitation is interpreted as, “ includes a plurality of target instruction pointers.”
Claim 7 recites, at line 4, “receives input data primarily from.” This is relative term involving a term of degree. The specification does not provide any standard for what qualifies as less common. Similarly, a person having ordinary skill in the art would be unable to determine how much input data must be received to satisfy this requirement.
Claims 2-7 and 10-15 are rejected as depending from rejected base claims and failing to cure the indefiniteness of those base claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Publication No. 2012/0303933 by Manet et al. (hereinafter referred to as “Manet”).
Regarding claim 1, Manet discloses:
a processing element array of a processor, comprising: a plurality of processing elements, each of the plurality of processing elements including at least one instruction register, a control unit, at least one arithmetic logic unit, and one or more storage elements, and being configured to store, decode and execute an instruction (Manet discloses, at Figure 2 and related description, a processor having an array of tiles, each having private instruction and data storage and at least one execution unit, which discloses a plurality of processing elements including at least one instruction register, one or more storage elements, at least one arithmetic or logic unit, and being configured to store and execute an instruction. As disclosed at Figure 10 and related description, the tiles are controlled by tile controllers, which discloses a control unit. As disclosed at Figure 12 and related description, tiles perform local decode, which discloses being configured to decode an instruction.);
wherein each of the at least one instruction registers and each of the at least one storage elements are configured to be writable from one or more data buses (Manet discloses, at Figure 6 and related description, communicating inputs and outputs using operand and results buses, which discloses the instruction register and the storage elements are configured to be writable from one or more data buses.); and
the arithmetic logic unit is configured to receive input from one of the at least one storage elements and to output a result to one or more other processing elements of the processing element array via the one or more data buses (Manet discloses, at Figure 7 and related description, processing input and outputting results to other tiles, which discloses, the arithmetic or logic unit is configured to receive input from one of the storage elements and to output a result to one or more other processing elements of the array of processing elements via the one or more data buses.);
an instruction register of a first processing element of the plurality of processing elements supports a plurality of target instruction pointers, defining respective logical connections between the first processing element and one or more other processing elements of the plurality of processing elements (Manet discloses, at Figure 2 and related description, instruction storage, which discloses an instruction register of a first processing element of the plurality of processing elements supports a plurality of target instruction pointers. As disclosed at Figure 1 and related description, the instructions communicate with other processing elements, which discloses the target instruction pointers defining respective logical connections between the first processing element and one or more other processing elements of the plurality of processing elements.);
one or more of the plurality of target instruction pointers are configured for control flow coordination (Manet discloses at Figure 2 and related description, the instructions include branch instruction, which discloses being configured for control flow coordination.); and
one or more of the plurality of target instruction pointers are configured for dataflow coordination (Manet discloses at Figure 2 and related description, the instructions include arithmetic and memory instructions, which discloses being configured for dataflow coordination.).
Regarding claim 2, Manet discloses the elements of claim 1, as discussed above. Manet also discloses:
the at least one arithmetic logic unit is configured to pass the result to one or more storage elements of the one or more other processing elements of the processing element array (Manet discloses, at Figure 7 and related description, processing input and outputting results to other tiles, which discloses, the arithmetic or logic unit is configured to pass the result to one or more storage elements of the other processing elements of the array of processing elements.).
Regarding claim 3, Manet discloses the elements of claim 1, as discussed above. Manet also discloses:
each of the plurality of processing elements includes a third storage element writable from the one or more data buses and a multiplexer intermediate a first storage element and one of the at least one arithmetic-logic units, the multiplexer being configured to receive inputs from the first and third storage elements and to pass selected outputs to the one of the at least one arithmetic-logic units (Manet discloses, at Figure 6 and related description, being coupled to three tiles, which discloses each of the processing elements includes a third storage element writable from the data bus. As disclosed at Figure 3(b) and related description, the couplings include registers and multiplexers, which discloses a multiplexer intermediate the first storage element and the arithmetic-logic unit, the multiplexer being configured to receive inputs from the first and third storage elements and to pass selected outputs to the arithmetic-logic unit elements.).
Regarding claim 4, Manet discloses the elements of claim 1, as discussed above. Manet also discloses:
each of the plurality of processing elements includes a control unit configured such that when an instruction encodes a conditional branch, the control unit determines a branch decision based on a send type of the instruction encoding the conditional branch and the result outputted by one of the at least one arithmetic-logic units being zero (Manet discloses, at Figure 10 and related description, the tiles are controlled by tile controllers and include branch units, which discloses a control unit and determining, for conditional branches, a branch decision based on a send type of the instruction. As disclosed at ¶ [0124], conditional branches use flags to determine their outcome, which discloses the result outputted by the arithmetic-logic unit being zero.).
Regarding claim 5, Manet discloses the elements of claim 1, as discussed above. Manet also discloses:
the instructions of each of the plurality of processing elements encode operations that require no intermediate translation into microinstructions before execution (Manet discloses, at Figure 5 and related description, an instruction format that is executed, which discloses the instructions encode operations that are basic enough to require no intermediate translation into microinstructions before execution.).
Regarding claim 6, Manet discloses the elements of claim 1, as discussed above. Manet also discloses:
the instructions of each of the plurality of processing elements have respective formats that facilitate fetching and decoding (Manet discloses, at Figure 5 and related description, an instruction format that is executed, which discloses the instructions have respective formats that facilitate simple fetching and decoding.).
Regarding claim 7, Manet discloses the elements of claim 1, as discussed above. Manet also discloses:
the instructions of each of the plurality of processing elements support a set of operand types such that each of the plurality of processing elements receives input data primarily from two storage elements that are statically associated with the respective processing element (Manet discloses, at Figure 5 and related description, an instruction format that has two input operands, which discloses each of the processing elements receives input data primarily from two storage elements that are statically associated with the respective processing element.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Manet in view of US Publication No. 2012/0131309 by Johnson et al. (hereinafter referred to as “Johnson”).
Regarding claim 10, Manet discloses the elements of claim 1, as discussed above. Manet also discloses:
an S bus that constitutes the one or more data buses (Manet discloses, at Figure 6 and related description, communicating inputs and outputs using operand and results buses, which discloses an S bus that constitutes the data bus.); and
…connects an external message bus to the S bus of the fabric tile (Manet discloses, at Figure 2 and related description, receiving information from instruction caches and data caches, which discloses an external message bus connected to the S bus of the fabric cell.);
the S bus implements the datapath of the plurality of processing elements, and facilitates data exchange between the plurality of processing elements… (Manet discloses, at Figure 6 and related description, communicating inputs and outputs using operand and results buses, which discloses the S bus implements the datapath of the processing elements, and facilitates data exchange between the processing elements.);
…forward instructions to the plurality of processing elements, coordinate fragment instance eviction and restoring locally, and assist the plurality of processing elements during the execution of communication and fragment instance management instructions (Manet discloses, at Figure 11 and related description, forwarding instructions to the processing elements and managing instructions, which discloses assist the processing elements during the execution of communication and fragment instance management instructions. Manet also discloses, at ¶ [0082], performing flushes and, at ¶ [0093], performing restores.).
Manet does not explicitly disclose a tile interface node that connects and facilitates and comprises a plurality of message registers.
However, in the same field of endeavor (e.g., multicore processing) Johnson discloses:
an interface node and message bus (Johnson discloses, at Figure 17 and related description, a control node that implements system-wide messaging on a message bus, which discloses a plurality of message registers. See also, e.g., ¶ [0338], which discloses communicating through registers.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Manet to include the interface node and messaging disclosed by Johnson in order to facilitate parallel processing by minimizing the cost of data communications. See Johnson, ¶ [0331].
Regarding claim 11, Manet discloses the elements of claim 10, as discussed above. Manet also discloses:
one or more S/T links for connecting the S bus to respective S buses of one or more adjacent fabric tiles via respective T links (Manet discloses, at Figure 2 and related description, links coupling adjacent clusters, which discloses one or more S/T links for connecting the S bus to respective S buses of one or more adjacent fabric cells or tiles via respective T links.).
Regarding claim 12, Manet discloses the elements of claim 11, as discussed above. Manet also discloses:
…a plurality of like fabric tiles (Manet discloses, at Figure 2 and related description, links coupling adjacent clusters, which discloses a plurality of like fabric cells or tiles.).
Manet does not explicitly disclose the interface node interfacing the aforementioned plurality of fabric cells or tiles.
However, in the same field of endeavor (e.g., multicore processing) Johnson discloses:
an interface node for a plurality of partitions (Johnson discloses, at Figure 17 and related description, a control node that interfaces a plurality of partitions.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Manet to include the interface node and messaging disclosed by Johnson in order to facilitate parallel processing by minimizing the cost of data communications. See Johnson, ¶ [0331].
Regarding claim 13, Manet discloses the elements of claim 10, as discussed above. Manet also discloses:
…a fragment instance manager and a fragment instance table (Manet discloses, at ¶ [0138] et seq., mapping fragments to tiles, which discloses a fragment instance manager and a fragment instance table.); and
a memory (Manet discloses, at ¶ [0138] et seq., memory.).
Manet does not explicitly disclose a message bus.
However, in the same field of endeavor (e.g., multicore processing) Johnson discloses:
a message bus (Johnson discloses, at Figure 17 and related description, a message bus.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Manet to include the message bus disclosed by Johnson in order to facilitate parallel processing by minimizing the cost of data communications. See Johnson, ¶ [0331].
Claim 14 is are rejected under 35 U.S.C. 103 as being unpatentable over Manet in view of Jonson in view of US Publication No. 2023/0109990 by Pappu et al. (hereinafter referred to as “Pappu”).
Regarding claim 14, Manet discloses the elements of claim 13, as discussed above. Manet also discloses:
the processor …[supports] linkage of a plurality of tiles (Manet discloses, at ¶ [0135], dynamic spatial relocation, which discloses implementing dynamic tiling so as to support linkage of a plurality of tiles.).
Manet does not explicitly disclose implementing dynamic tiling.
However, in the same field of endeavor (e.g., processors) Pappu discloses:
enabling or disabling execution units (Pappu discloses, at ¶ [0283], enabling or disabling execution units based on computational requirements, which discloses dynamic tiling.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Manet to include dynamic tiling, as disclosed by Pappu, in order to improve performance by increasing parallelism and increasing utility by providing flexibility.
Claim 15 is are rejected under 35 U.S.C. 103 as being unpatentable over Manet in view of Jonson in view of Pappu in view of Official Notice.
Regarding claim 15, Manet discloses the elements of claim 13, as discussed above. Manet does not explicitly disclose the processor implements dynamic tiling whereby the number of processing elements per fabric tile divides the maximum number of instructions evenly such that, when fragments beyond the limit of a single fibric tile enter or leave the fabric tile, adjacent fabric tiles are linked or unlinked on the fly.
However, in the same field of endeavor (e.g., processors) Pappu discloses:
enabling or disabling execution units (Pappu discloses, at ¶ [0283], enabling or disabling execution units based on computational requirements, which discloses dynamic tiling whereby the number of processing elements per fabric tile divides the maximum number of instructions … such that, when fragments beyond the limit of a single fibric tile enter or leave the fabric tile, adjacent fabric tiles are linked or unlinked on the fly..).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Manet to include dynamic tiling, as disclosed by Pappu, in order to improve performance by increasing parallelism and increasing utility by providing flexibility.
Manet, as modified, does not disclose that the aforementioned dividing is even. However, the Examiner takes official notice that it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the number of processing elements divide evenly into the maximum number of instructions in order to improve performance by reducing idle processing units.
Response to Arguments
On page 9 of the response filed December 18, 2025 (“response”), the Applicant argues, “The drawings stand objected allegedly because of the minor informalities. In response, Applicant files concurrently herewith a Replacement Sheets to make requested changes suggested by the Examiner. Accordingly, Applicant requests that this objection be withdrawn.”
Though fully considered, the Examiner respectfully disagrees. No replacement drawings were received. Accordingly, the Applicant’s arguments are deemed unpersuasive.
On pages 11-12 of the response the Applicant argues, “Applicant contends that none of the cited references, taken singly or combined, discloses, suggests, or renders obvious independent claim 1, particularly in the features highlighted above. For example, Applicant submits that although Manet may disclose a processor including number of elements, Manet, does not explicitly teach the newly added limitations now required in the claimed invention. In this regard, Applicant directs the Examiner's attention to page 13 of Office Action. The Examiner relies on paragraph [0152] of Monet for allegedly teaching the original limitations recited in claim 9. Applicant respectfully disagrees. In contrast, Manet uses separate and very different mechanisms for dataflow and control flow. Manet uses DCLs (data communication links) for dataflow (cf. Manet abstract) and branches for local control flow. Original claim 9 (now incorporated into independent claim 1) specifies that instruction pointers are used for dataflow coordination and control flow coordination, but in Manet that mechanism is used only for control flow coordination. Data flow does not work using instruction pointers, but rather using DCLs that are not statically bound to PEs, thus requiring data addressing at data source and data sink. In the architecture of the present invention, the addressing is done at the data source instruction/PE, and the data is directly written to the data sink (destination) instruction/PE. As a result, Manet fails to disclose the newly amended claim 1, as the architectures of Manet and of the present invention (as defined in amended claim 1) differ fundamentally. Furthermore, Johnson fails to remedy the above-noted deficiencies in Monet.”
Though fully considered, the Examiner respectfully disagrees. Manet discloses that the DCLs are used for communication and that all instructions take their operands from the DCLs. See, e.g., ¶ [0117]. This includes both branch instructions as well as dataflow instructions, such as arithmetic and memory instructions. See, e.g., ¶ [0102] et seq. Accordingly, the Applicant’s arguments are deemed unpersuasive.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure.
US 20230315670 by Persson discloses dynamically partitioning processing tiles.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/
Primary Examiner, Art Unit 2183