DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE AND METHOD HAVING LAMINATING FILMS TO PREVENT FILM PEELING.
Claim 7 is objected to because of the following informalities: Claim 7 recites “the surface protective film” without antecedent basis to “a surface protective film.” Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, and 8-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LIN et al. (US 20170256496 A1, hereinafter Lin)
With regards to claim 1, Lin discloses a semiconductor device (FIG. 3) comprising:
a silicon substrate; (silicon substrate 100)
an insulating film (insulating layer 210) laminated on the silicon substrate;
at least one or more wiring patterns (first portion 220A) formed on the insulating film;
an interlayer film (protection layer 250) laminated between the one or more wiring patterns; and
a conductive protective film (conducting structure 270) embedded in an interlayer film opening formed in the interlayer film. (See FIG. 3)
With regards to claim 4, Lin discloses the semiconductor device according to claim 1, wherein the conductive protective film is formed to be wider than a width of the wiring pattern, and a peripheral edge of the interlayer film opening is covered with the conductive protective film via the interlayer film. (see FIG. 3, where the structure 270 is wider in a direction away from the substrate 100 and the structure 270 covers an edge of layer 250)
With regards to claim 8, Lin discloses the semiconductor device according to claim 1, wherein a linear expansion coefficient of the conductive protective film has a relationship that is larger than a linear expansion coefficient of the insulating film and smaller than a linear expansion coefficient of a material of the wiring pattern. (Paragraph [0063]: “the conductive structures 270 include tin, lead, copper, gold, nickel,…” where Nickel matches the material listed in the Specification, and would inherently have the necessary linear expansion coefficient.)
With regards to claim 9, Lin discloses the semiconductor device according to claim 1, wherein the conductive protective film includes titanium (Ti), nickel (Ni), (Paragraph [0063]: “the conductive structures 270 include tin, lead, copper, gold, nickel,…”) or an alloy containing these elements.
With regards to claim 10, Lin discloses the semiconductor device according to claim 1, wherein the conductive protective film has a laminated structure including at least one or more layers of the titanium (Ti), nickel (Ni), or alloy including these elements. (Paragraph [0063]: “the conductive structures 270 include tin, lead, copper, gold, nickel,…”)
With regards to claim 11, Lin discloses a method for manufacturing a semiconductor device, (FIG. 3) the method comprising:
a step of forming a silicon substrate; (silicon substrate 100)
a step of forming an insulating film (insulating layer 210) on an upper surface of the silicon substrate;
a step of forming at least one or more wiring patterns (first portion 220A) on an upper surface of the insulating film;
a step of forming an interlayer film (protection layer 250) on an upper surface of the wiring pattern;
a step of forming an interlayer film opening (opening comprising electrode 270, see FIGS. 2C-3) having a predetermined shape in the interlayer film; and
a step of forming a conductive protective film (electrode 270) on an upper surface of the interlayer film and embedding the conductive protective film in the interlayer film opening. (see FIG. 3)
With regards to claim 12, Lin discloses the method for manufacturing a semiconductor device according to claim 11, wherein the step of forming the silicon substrate has a step of bonding a circuit substrate (circuit substrate having optical element 150 and layer 130) having a wiring pattern (pattern 220A) on a lower surface of the silicon substrate, and providing a through-Si electrode (pattern 230A) coupled to the wiring pattern from the upper surface of the silicon substrate. (See FIG. 3)
With regards to claim 13, Lin discloses an electronic apparatus having a semiconductor device (FIG. 3) including:
a silicon substrate; (silicon substrate 100)
an insulating film (insulating layer 210) laminated on the silicon substrate;
at least one or more wiring patterns (first portion 220A) formed on the insulating film;
an interlayer film (protection layer 250) laminated between the one or more wiring patterns; and
a conductive protective film (conducting structure 270) embedded in an interlayer film opening formed in the interlayer film.
Allowable Subject Matter
Claims 2-3 and 5-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812
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