Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
1. Applicant’s arguments, filed February 25th, 2026, with respect to the claim objections and 35 U.S.C. 101 rejections have been fully considered and are persuasive in light of the claim amendments. The claim objections and 35 U.S.C. 101 rejections have been withdrawn.
2. Applicant's arguments filed February 25th, 2026, with respect to the 35 U.S.C. 103 rejections have been fully considered but they are not persuasive.
Applicant first argues, with respect to the independent claims, that Alexander fails to teach the claim limitations as the “non-accumulating matrix production instruction…is not an accumulate instruction specifying an accumulate operation”, and “there is no suggestion that the load-store instruction affects the operation performed by the arithmetic instruction, let alone causes an accumulate instruction to perform a non-accumulating variant”.
In response to the above argument, Examiner respectfully disagrees. Applicant’s arguments are primarily based upon alleged features of the invention not found within the language of the claims. Claim 1, and other independent claims, merely require that a decoder decodes a zero vectors instruction (which Alexander is not relied upon for teaching specifically) and a subsequent accumulate instruction, and then to produce result data by performing a “non-accumulating variant of an accumulate operation specified by the accumulate instruction”. It does not require that the zero vectors instruction and accumulate instruction are in any way “combined” as stated by Applicant, nor does it require that the first instruction “affects the operation performed by the arithmetic instruction”. Therefore, the disclosure of Alexander, which states that the processor may generate results via “a non-accumulating matrix product instruction” does disclose the features of the invention that are actually found within the language of the claims, and the arguments are not considered persuasive.
Applicant then argues, with respect to claim 1 and the Dasgupta reference, that Dasgupta fails to teach a “zero vectors” instruction that “identif[ies] multiple vectors of data elements”.
In response to the above argument, Examiner respectfully disagrees. Applicant is again arguing based upon alleged features of the invention not found within the language of the claims. In claim 1, the decoder circuitry is merely recited as decoding a zero vectors instruction that identifies data elements in a two-dimensional array. There is no limitation present in claim 1 which explains what a “zero vectors” instruction performs, and as “zero vectors instruction” is not a precise term of art, the broadest reasonable interpretation is consistent with the disclosure of Dasgupta, which teaches explicit instructions for zeroing elements of a two-dimensional array (Dasgupta [0069-0070]). Therefore, the arguments are not considered persuasive and the rejection is maintained.
Finally, Applicant argues that Dasgupta fails to teach the “zero vectors instruction” of claim 8, as Dasgupta fails to teach the instruction “identifying multiple vectors of data elements and causing those multiple vectors to be set to logic value zero”, as required by the language of claim 8.
In response to the above argument, Examiner respectfully disagrees. Paragraphs [0069-0070] of the Dasgupta explicitly state that “tile operations will zero any rows and columns beyond the dimensions specified by the tile configuration”, and “an operation writing FP32 elements would write each of the first 10 rows with 12*4 bytes with output/result data and zero the remaining 4*4 bytes in each row”, and “fully zero any rows after the first 10 configured rows” (emphasis added by Examiner). As “zero vectors instruction” is not a precise term of art, the broadest reasonable interpretation is consistent with the disclosure of Dasgupta, in which these exemplary tile operations zero two-dimensional arrays (rows and columns) of data elements (the “FP32 elements”) according to the configuration of the matrix tiles and the exemplary instructions [Dasgupta [0025] states that two-dimensional data structures in the disclosure are referred to as tiles]. Therefore, the arguments are not considered persuasive and the rejection is maintained.
The rest of Applicant’s arguments are based on the arguments addressed above. Above responses are thus applicable.
Examiner recommends amending the independent claims to more clearly identify the nature of the “zero vectors instruction” as explained on pages 9-10 of the Remarks, which describe more specifically the nature of the instruction as it relates to the specification of the instant application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Alexander et al (US 2020/0210187, herein Alexander) in view of Dasgupta et al (US 2020/0410038, herein Dasgupta).
Regarding claim 1, Alexander teaches an apparatus comprising:
processing circuitry configured to perform operations ([0072], execution pipeline);
instruction decoder circuitry configured to decode instructions to control the processing circuitry to perform the operations specified by the instructions ([0075], decode stage); and
storage comprising storage elements configured to store data elements comprising a plurality of vectors of data elements, where each vector is one dimensional ([0149], [0160-0161], input vectors of data elements);
wherein the instruction decoder circuitry is configured, in response to decoding both: a vector instruction that identifies multiple vectors of data elements, and a subsequent accumulate instruction arranged to operate on the identified multiple vectors of data elements, to control the processing circuitry to perform a non-accumulating variant of an accumulate operation specified by the accumulate instruction to produce result data elements for storing in the identified multiple vectors within the storage ([0146], [0171], non-accumulating version of matrix product instruction utilized when necessary to output results or stream results back to memory).
Alexander fails to teach the storage being arranged to store at least one two dimensional array of data elements accessible to the processing circuitry when performing the operations, each two dimensional array of data elements, wherein the instruction is a zero vectors instruction that operates on a given two dimensional array of data elements within the array storage.
Dasgupta teaches an apparatus comprising processing circuitry and array storage arranged to store at least one two dimensional array of data elements accessible to the processing circuitry when performing operations, each a two dimensional array of data elements, wherein a zero vectors instruction operates on a given two dimensional array of data elements within the array storage (Abstract, [0165-0166], performing matrix operations on two-dimensional data array of vectors & [0069], [0150-0151], [0255], zeroing instructions and writemasks of result location).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Alexander and Dasgupta to utilize zeroing techniques and multidimensional arrays of data elements. While Alexander does not explicitly state that the exemplary input vectors may be organized into two-dimensional arrays, one of ordinary skill in the art would understood that a matrix is inherently a data structure with two or more dimensions, and both Alexander and Dasgupta disclose the execution of matrix operations within the processor. Therefore, the combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and would have been obvious to one of ordinary skill in the art.
Regarding claim 2, the combination of Alexander and Dasgupta teach the apparatus as claimed in claim 1, wherein: the array storage comprises a plurality of array vector registers extending in a first array direction (Dasgupta [0076], two dimensional register structures), and the identified multiple vectors within the array storage are provided by a group of multiple array vector registers of the array storage (Dasgupta [0076]); the given two dimensional array of data elements comprises the data elements stored within the group of multiple array vector registers (Dasgupta [0076], [0085], input data elements of 2D data structure); the subsequent accumulate instruction specifies a processing operation that includes an accumulate operation to be performed on the identified multiple vectors of data elements; and the zero vectors instruction is used in combination with the subsequent accumulate instruction to enable performance by the processing circuitry of a nonaccumulating variant of the processing operation (Dasgupta [0069], [0150-0151], [0255], zeroing instructions and writemasks of result location & Alexander [0146], [0171], non-accumulating version of matrix product instruction utilized when necessary to output results or stream results back to memory).
Regarding claim 3, the combination of Alexander and Dasgupta teach the apparatus as claimed in claim 1, wherein the zero vectors instruction comprises a vector identification field used to identify the multiple vectors of data elements of the given two dimensional array of data elements within the array storage (Dasgupta [0069], [0150-0151], [0255], identifying which elements to zero based on writemask fields).
Regarding claim 4, the combination of Alexander and Dasgupta teach the apparatus as claimed in claim 1, wherein the zero vectors instruction comprises a predicate field to identify predicate information used to identify which storage elements within the multiple identified vectors are to be set to the logic zero value (Dasgupta [0323], write mask register used to predicate result vector writes & [0069], [0150-0151], [0255], zeroing).
Regarding claim 5, the combination of Alexander and Dasgupta teach the apparatus as claimed in claim 4, wherein the zero vectors instruction further comprises a size field to identify a size of each data element within the multiple identified vectors (Dasgupta [0155], [0243-0244], size of element or vector identified by instruction template).
Claim 6 refers to a method embodiment of the apparatus embodiment of claim 1. Therefore, the above rejection for claim 1 is applicable to claim 6.
Claim 7 refers to a program embodiment of the apparatus embodiment of claim 1. Therefore, the above rejection for claim 1 is applicable to claim 7.
Regarding claim 8, Alexander teaches an apparatus comprising:
processing circuitry configured to perform operations ([0072], execution pipeline);
instruction decoder circuitry configured to decode instructions to control the processing circuitry to perform the operations specified by the instructions ([0075], decode stage); and
storage comprising storage elements configured to store data elements comprising a plurality of vectors of data elements, where each vector is one dimensional ([0149], [0160-0161], input vectors of data elements);
wherein the instruction decoder circuitry is configured, in response to decoding a vector instruction that identifies multiple vectors of data elements, to control the processing circuitry to perform the operations and store the result data elements of the identified multiple vectors ([0094-0095], [0171], performing and outputting results of matrix operations on input vector elements).
Alexander fails to teach the storage being arranged to store at least one two dimensional array of data elements accessible to the processing circuitry when performing the operations, each two dimensional array of data elements, wherein the instruction is a zero vectors instruction that operates on a given two dimensional array of data elements within the array storage, wherein the zero vectors instruction sets to a logic zero value the storage elements.
Dasgupta teaches an apparatus comprising processing circuitry and array storage arranged to store at least one two dimensional array of data elements accessible to the processing circuitry when performing operations, each a two dimensional array of data elements, wherein a zero vectors instruction operates on a given two dimensional array of data elements within the array storage, wherein the zero vectors instruction sets to a logic zero value the storage elements (Abstract, [0165-0166], performing matrix operations on two-dimensional data array of vectors & [0069], [0150-0151], [0255], zeroing instructions and writemasks of result location).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Alexander and Dasgupta to utilize zeroing techniques and multidimensional arrays of data elements. While Alexander does not explicitly state that the exemplary input vectors may be organized into two-dimensional arrays, one of ordinary skill in the art would understood that a matrix is inherently a data structure with two or more dimensions, and both Alexander and Dasgupta disclose the execution of matrix operations within the processor. Therefore, the combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and would have been obvious to one of ordinary skill in the art.
Claim 9 refers to a method embodiment of the apparatus embodiment of claim 8. Therefore, the above rejection for claim 8 is applicable to claim 9.
Claim 10 refers to a program embodiment of the apparatus embodiment of claim 8. Therefore, the above rejection for claim 8 is applicable to claim 10.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J METZGER whose telephone number is (571)272-3105. The examiner can normally be reached Monday-Friday 8:30-5.
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/MICHAEL J METZGER/ Primary Examiner, Art Unit 2183
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