Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
1. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on August 6th, 2026 has been entered.
Response to Arguments
2. Applicant’s arguments filed August 6th, 2026, with respect to the rejections of claims 1-7 have been fully considered and are persuasive in light of the claim amendments. The rejections of claims 1-7 have been withdrawn.
3. Applicant’s arguments filed August 6th, 2026, with respect to the rejections of claims 8-10 have been fully considered but they are not persuasive.
As Applicant’s arguments are directed toward limitations of the claims added via amendment, they will be addressed in the rejections below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Alexander et al (US 2020/0210187, herein Alexander) in view of Dasgupta et al (US 2020/0410038, herein Dasgupta).
Regarding claim 8, Alexander teaches an apparatus comprising:
processing circuitry configured to perform operations ([0072], execution pipeline);
instruction decoder circuitry configured to decode instructions to control the processing circuitry to perform the operations specified by the instructions ([0075], decode stage); and
storage comprising storage elements configured to store data elements comprising a plurality of vectors of data elements, where each vector is one dimensional ([0149], [0160-0161], input vectors of data elements);
wherein the instruction decoder circuitry is configured, in response to decoding a vector instruction that identifies multiple vectors of data elements, to control the processing circuitry to perform the operations and store the result data elements of the identified multiple vectors ([0094-0095], [0171], performing and outputting results of matrix operations on input vector elements).
Alexander fails to teach the storage being arranged to store at least one two dimensional array of data elements accessible to the processing circuitry when performing the operations, each two dimensional array of data elements, wherein the instruction is a zero vectors instruction comprising a vector identification field that operates on a given two dimensional array of data elements within the array storage, wherein the zero vectors instruction sets to a logic zero value the storage elements.
Dasgupta teaches an apparatus comprising processing circuitry and array storage arranged to store at least one two dimensional array of data elements accessible to the processing circuitry when performing operations, each a two dimensional array of data elements, wherein a zero vectors instruction comprising a vector identification field ([0248-0249], identify source operands with register index field) operates on a given two dimensional array of data elements within the array storage, wherein the zero vectors instruction sets to a logic zero value the storage elements (Abstract, [0165-0166], performing matrix operations on two-dimensional data array of vectors & [0069], [0150-0151], [0255], zeroing instructions and writemasks of result location).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Alexander and Dasgupta to utilize zeroing techniques and multidimensional arrays of data elements. While Alexander does not explicitly state that the exemplary input vectors may be organized into two-dimensional arrays, one of ordinary skill in the art would understood that a matrix is inherently a data structure with two or more dimensions, and both Alexander and Dasgupta disclose the execution of matrix operations within the processor. Therefore, the combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and would have been obvious to one of ordinary skill in the art.
Claim 9 refers to a method embodiment of the apparatus embodiment of claim 8. Therefore, the above rejection for claim 8 is applicable to claim 9.
Claim 10 refers to a program embodiment of the apparatus embodiment of claim 8. Therefore, the above rejection for claim 8 is applicable to claim 10.
Allowable Subject Matter
5. Claims 1-7 are allowed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sade (US 11,669,326) discloses a processor that zeroes data elements of a pair of matrices identified by an operand.
Sade (US 2019/0042256) discloses a processor that performs a zeroing instruction on data elements of matrices identified by an operand.
Taunton (US 2005/0071415) discloses a processor that combines variants of instructions to zero an accumulator from a product value.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J METZGER whose telephone number is (571)272-3105. The examiner can normally be reached Monday-Friday 8:30-5.
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/MICHAEL J METZGER/ Primary Examiner, Art Unit 2183
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