Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-8 and 10-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by “Reynov” (US 2011/0155434).
Regarding claim 1, Reynov anticipates 1. A circuit board, comprising a plurality of array connection points arranged in a connection point array, and a plurality of array holes arranged in a hole array, with at least part of the plurality of array connection points electrically connected to at least one of the plurality of array holes (Figs. 2A-2B, 3A-3B, 4-5, [0016]-[0020]; the printed circuit board PCB comprising ball-grid-array BGA footprint elements 205 which are arranged in a connection point array, and electrically connected to a respective via 220 of the plurality of vias 220);
wherein, a standard array and a virtual array, which have same structures, are defined in the circuit board, and corresponding structural directions in the standard array and the virtual array are parallel to each other (Figs. 2A-2B, 3A-3B, 4-5, [0016]-[0020]; the plurality of vias 220 is a standard array and the array of the ball grid array pads 215 is a virtual array, which have same structures, are defined in the circuit board, and corresponding structural directions in the standard array and the virtual array are parallel to each other);
each of the plurality of array connection points is located at a corresponding standard point position in the standard array (Figs. 2A-2B, 3A-3B, 4-5, [0016]-[0020]; each of the plurality of ball-grid-array BGA footprint elements 205 is located at a corresponding standard point position in the standard array);
and the hole array comprises a plurality of standard array holes and at least one offset array hole (Figs. 2A-2B, 3A-3B, 4-5, [0016]-[0020]; the hole array comprises a plurality of standard array vias 220 and at least one offset via 220 in Fig. 2B);
each of the plurality of standard array holes is located at a corresponding virtual point position in the virtual array (Figs. 2A-2B, 3A-3B, 4-5, [0016]-[0020]; each of the plurality of vias 220 is located at a corresponding virtual point position in the virtual array of the ball grid array pads 215);
and a first side of each offset array hole is adjacent to a first lead, and the offset array hole deviates from a corresponding virtual point position in the virtual array towards a second side by a first predetermined distance, with the second side being an opposite side relative to the first side (Figs. 2A-2B, 3A-3B, 4-5, [0016]-[0020]; a first side of each offset via 220 is adjacent to a routing channel 300 which is a first lead, and the offset via 220 deviates from a corresponding virtual point position in the virtual array of the ball grid array pads 215 towards a second side by a first predetermined distance, with the second side being an opposite side relative to the first side, Fig. 3A).
Regarding claim 2, Reynov anticipates 2. The circuit board of claim 1, wherein the hole array comprises a plurality of rows and a plurality of columns; and each first lead is disposed between two adjacent columns of array holes (Figs. 2A-2B, 3A-3B, 4-5, [0016]-[0020]; the hole array of the plurality of vias 220 comprises a plurality of rows and a plurality of columns; and each routing channel 300 is disposed between two adjacent columns of array vias 220).
Regarding claim 3, Reynov anticipates 3. The circuit board of claim 1, wherein the standard array is a matrix, and rows of the matrix are perpendicular to columns of the matrix (Figs. 2A-2B, 3A-3B, 4-5, [0016]-[0020]; the standard array of the array of the plurality of vias 220 is a matrix, and rows of the matrix are perpendicular to columns of the matrix).
Regarding claim 5, Reynov anticipates 5. The circuit board of claim 1, wherein the hole array comprises at least one offset hole group; and each offset hole group comprises two adjacent offset array holes, and the first side of any one of the two adjacent offset array holes is adjacent to the other one of the two adjacent offset array holes (Figs. 2A-2B, 3A-3B, 4-5, [0016]-[0020]; the hole array of the plurality of vias 220 comprises at least one offset hole group, Fig. 3A, and each offset hole group comprises two adjacent offset array via 220 holes, and the first side of any one of the two adjacent offset array via 220 holes is adjacent to the other one of the two adjacent offset array via 220 holes).
Regarding claim 6, Reynov anticipates 6. The circuit board of claim 5, wherein at least part of adjacent offset array holes is provided with one lead therebetween, and the lead serves as first leads of both two adjacent offset array holes (Figs. 2A-2B, 3A-3B, 4-5, [0016]-[0020]; part of adjacent offset array via 220 holes is provided with one routing channel 300 therebetween, and the routing channel 300 serves as first leads of both two adjacent offset array via 220 holes, Fig. 3A).
Regarding claim 7, Reynov anticipates 7. The circuit board of claim 5, wherein at least part of adjacent offset array holes is provided with two leads therebetween, and the two leads respectively serve as first leads of two adjacent offset array holes (Figs. 2A-2B, 3A-3B, 4-5, [0016]-[0020]; part of adjacent offset array via 220 holes is provided with two routing channels 300 therebetween, and the two routing channels 300 respectively serve as first leads of two adjacent offset array via 220 holes, Fig. 3A).
Regarding claim 8, Reynov anticipates 8. The circuit board of claim 5, wherein at least part of adjacent offset array holes is provided with one lead therebetween, and the lead serves as first leads of both two adjacent offset array holes (Figs. 2A-2B, 3A-3B, 4-5, [0016]-[0020]; part of adjacent offset array via 220 holes is provided with one routing channel 300 therebetween, and the routing channel 300 serves as first leads of both two adjacent offset array via 220 holes, Fig. 3A);
and at least part of adjacent offset array holes is provided with two leads therebetween, and the two leads respectively serve as first leads of two adjacent offset array holes (Figs. 2A-2B, 3A-3B, 4-5, [0016]-[0020]; part of adjacent offset array via 220 holes is provided with two routing channels 300 therebetween, and the two routing channels 300 respectively serve as first leads of two adjacent offset array via 220 holes, Fig. 3A).
Regarding claim 10, Reynov anticipates 10. The circuit board of claim 1, wherein at least part of offset array holes are back-drilled holes (The limitations regarding the back-drilled holes involves a back-drilling method to form the array holes which is a process limitation in a product claim and is treated in accordance with MPEP 2113. As this process limitation uses a product structure that is the same as the array holes of Reynov, this claim is therefore anticipated by Reynov).
Regarding claim 11, Reynov anticipates 11. The circuit board of claim 10, wherein the hole array comprises at least one offset hole group; each offset hole group comprises two adjacent offset array holes, and the first side of any one of the two adjacent offset array holes is adjacent to the other one of the two adjacent offset array holes (Figs. 2A-2B, 3A-3B, 4-5, [0016]-[0020]; the hole array of the plurality of vias 220 comprises at least one offset hole group, Fig. 3A, and each offset hole group comprises two adjacent offset array via 220 holes, and the first side of any one of the two adjacent offset array via 220 holes is adjacent to the other one of the two adjacent offset array via 220 holes);
and the two adjacent offset array holes in each offset hole group are both back-drilled holes (The limitations regarding the back-drilled holes involves a back-drilling method to form the array holes which is a process limitation in a product claim and is treated in accordance with MPEP 2113. As this process limitation uses a product structure that is the same as the array holes of Reynov, this claim is therefore anticipated by Reynov).
Regarding claim 12, Reynov anticipates 12. The circuit board of claim 1, wherein the plurality of array connection points are pads for connection to a ball grid array (Figs. 2A-2B, 3A-3B, 4-5, [0016]-[0020]; each of the plurality of ball-grid-array BGA footprint elements 205 are ball grid array pads 215).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Reynov in view of “Eckert” (US 2023/0292447).
Regarding claim 9, Reynov discloses the claimed invention as applied to claim 1, above.
Reynov does not disclose the limitations of claim 9.
Eckert discloses 9. The circuit board of claim 1, wherein at least part of first leads are differential lines (Fig. 1, [0033]; a high speed differential pair of signaling traces in the form of surface wires, including a first wire 120 and a second wire 124).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Reynov’s circuit board with Eckert’s differential lines in order to result in a signal with a magnitude that is twice as large, as suggested by Eckert at [0024].
Claims 13-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Reynov.
Regarding claim 13, Reynov discloses the claimed invention as applied to claim 12, above.
Reynov discloses 13. The circuit board of claim 12, wherein virtual point positions corresponding to at least part of the plurality of array holes are positions of the pads (Figs. 2A-2B, 3A-3B, 4-5, [0016]-[0020]; the array of the ball grid array pads 215 are virtual point positions corresponding to the plurality of array via 220 holes),
and the at least part of the plurality of array holes are electrically connected to the pads having the positions coincident with positions of the at least part of the plurality of array holes (Figs. 2A-2B, 3A-3B, 4-5, [0016]-[0020]; part of the plurality of array via 220 holes are electrically connected to the ball grid array pad 215 having the positions coincident with positions of the at least part of the plurality of array via 220 holes).
Reynov does not disclose the first predetermined distance is smaller than a sum of a radius of a pad and a radius of an array hole.
It would have been an obvious matter of design choice to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Reynov’s ball-grid-array BGA footprint elements 205 such that the distance is smaller than a sum of a radius of a pad and a radius of an array hole. Although Reynov does not explicitly quantify the distance in terms of the sum of a radius of a pad and a radius of an array hole, Reynov, [0016]-[0019] provides several examples of the varying distances from the center of the via 220 to the center of the BGA pad 215. A person having ordinary skill would have constructed the distance to be smaller than the sum of a radius of the pad 215 and the radius of an array via 220 hole through routine experimentation.
Regarding claim 14, Reynov discloses the claimed invention as applied to claim 12, above.
Reynov discloses 14. The circuit board of claim 12, wherein virtual point positions corresponding to at least part of the plurality of array holes deviate from positions of the pads by a second predetermined distance (Figs. 2A-2B, 3A-3B, 4-5, [0016]-[0020]; virtual point positions of the ball grid array pads 215 corresponding to at least part of the plurality of array via 220 holes deviate from positions of the pads by a second predetermined distance),
and the at least part of the plurality of array holes are electrically connected to the pads through connecting leads (Figs. 2A-2B, 3A-3B, 4-5, [0016]-[0020]; the at least part of the plurality of array vias 220 holes are electrically connected to the ball grid array pads 215 through connecting leads).
Reynov does not disclose the second predetermined distance is greater than a sum of a radius of a pad and a radius of an array hole.
It would have been an obvious matter of design choice to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Reynov’s ball-grid-array BGA footprint elements 205 such that the distance is greater than a sum of a radius of a pad and a radius of an array hole. Although Reynov does not explicitly quantify the distance in terms of the sum of a radius of a pad and a radius of an array hole, Reynov, [0016]-[0019] provides several examples of the varying distances from the center of the via 220 to the center of the BGA pad 215. A person having ordinary skill would have constructed the distance to be greater than the sum of a radius of the pad 215 and the radius of an array via 220 hole through routine experimentation.
Regarding claim 15, Reynov discloses the claimed invention as applied to claim 1, above.
Reynov discloses 15. A circuit board assembly, comprising: the circuit board claim 1; and electronic device disposed on the circuit board, with at least part of the electronic devices electrically connected to array connection points (Abstract, [0001], [0004]; a ball grid array BGA device is an IC package is disposed on the BGA pads a printed circuit board).
Reynov does not disclose electronic devices disposed on the circuit board.
It would have been obvious matter of design choice to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Reynov’s circuit board with multiple electronic devices since it was well-known that a circuit board would have a plurality of electronic devices. Furthermore, it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. Therefore, it would have involved only routine skill in the art to have included an extra electronic device on Reynov’s circuit board.
Regarding claim 16, Reynov discloses the claimed invention as applied to claim 15, above.
Reynov discloses 16. The circuit board assembly of claim 15, wherein the hole array comprises a plurality of rows and a plurality of columns; and each first lead is disposed between two adjacent columns of array holes (Figs. 2A-2B, 3A-3B, 4-5, [0016]-[0020]; the hole array of the plurality of vias 220 comprises a plurality of rows and a plurality of columns; and each routing channel 300 is disposed between two adjacent columns of array vias 220).
Regarding claim 17, Reynov discloses the claimed invention as applied to claim 15, above.
Reynov discloses 17. The circuit board assembly of claim 15, wherein the standard array is a matrix, and rows of the matrix are perpendicular to columns of the matrix (Figs. 2A-2B, 3A-3B, 4-5, [0016]-[0020]; the standard array of the array of the plurality of vias 220 is a matrix, and rows of the matrix are perpendicular to columns of the matrix).
Regarding claim 19, Reynov discloses the claimed invention as applied to claim 15, above.
Reynov discloses 19. The circuit board assembly of claim 15, wherein the hole array comprises at least one offset hole group; and each offset hole group comprises two adjacent offset array holes, and the first side of any one of the two adjacent offset array holes is adjacent to the other one of the two adjacent offset array holes (Figs. 2A-2B, 3A-3B, 4-5, [0016]-[0020]; the hole array of the plurality of vias 220 comprises at least one offset hole group, Fig. 3A, and each offset hole group comprises two adjacent offset array via 220 holes, and the first side of any one of the two adjacent offset array via 220 holes is adjacent to the other one of the two adjacent offset array via 220 holes).
Regarding claim 20, Reynov discloses the claimed invention as applied to claim 19, above.
Reynov discloses 20. The circuit board assembly of claim 19, wherein at least part of adjacent offset array holes is provided with one lead therebetween, and the lead serves as first leads of both two adjacent offset array holes (Figs. 2A-2B, 3A-3B, 4-5, [0016]-[0020]; part of adjacent offset array via 220 holes is provided with one routing channel 300 therebetween, and the routing channel 300 serves as first leads of both two adjacent offset array via 220 holes, Fig. 3A).
Claims 4 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Reynov in view of “Benedict” (US 2023/0292436).
Regarding claim 4 and 18, Reynov discloses the claimed invention as applied to respective claims 1 and 15, above.
Reynov discloses second sides of at least part of offset array holes are adjacent to a second lead, an extension direction of the second lead is perpendicular to a direction pointing from first sides to the second sides (Figs. 2A-2B, 3A-3B, 4-5, [0016]-[0020]; second sides of at least part of offset array via 220 holes are adjacent to a second routing channel 300, an extension direction of the second routing channel 300 is perpendicular to a direction pointing from first sides to the second sides).
Reynov does not disclose the second lead forms bent structures at positions adjacent to the offset array holes, with the bent structures protruding in a direction away from the offset array holes.
Benedict discloses the second lead forms bent structures at positions adjacent to the offset array holes, with the bent structures protruding in a direction away from the offset array holes (Figs. 1-2, [0015], [0025], [0045], [0055]; the signal trace 312 forms bent structures at positions adjacent to the via 106 108 array holes, with the bent structures protruding in a direction away from the via 106 108 array holes).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Reynov’s circuit board with Benedict’s bent structures in order to modulate the separation lengths, thus reducing crosstalk, as suggested by Benedict at [0011].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANLEY TSO whose telephone number is (571)270-0723. The examiner can normally be reached Tu-Thurs 6am-6pm, alt M 6am-2pm.
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/STANLEY TSO/Primary Examiner, Art Unit 2847
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