DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on October 18, 2024, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5-6, 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (CN 109860160 A) and in further view of Yoshihara (US 20170092596 A1) and Hao et al. (CN 112510000 A)
Regarding Claim 1 – Yang teaches a low-inductance current-sharing power module (Fig 3; 141, 151; Yang states “enabling current sharing between the parallel chips” and “further reducing the parasitic inductance of the power module”), comprising a first chipset, a second chipset, positive electrodes, a negative electrode and an output electrode (Figs 2-4; 141/142, 151/152, 11, 12, 13); the first chipset is evenly arranged on an upper surface of the first copper-sheet area and is coupled to the second copper-sheet area through a first link device (Fig 4; 14, 15, 1421; Yang states “Two upper arm chip units are disposed on the upper arm copper layer 14” and “The arm diode chip surface bonding wire 1421 is connected to the lower arm copper layer 15”); the second chipset is evenly arranged on an upper surface of the second copper-sheet area (Fig 4; 15, 151/152; Yang states “two lower arm chip units are disposed on the lower arm copper layer 15”) and the positive electrode is coupled to the first copper-sheet area and extends outward (Figs 3, 6; 11, 14; Yang states “positive electrode lead portion 111 for connecting an external power source” and “positive electrode fillet 114 are connected to the upper arm copper layer 14”), and the output electrode is coupled to the second copper-sheet area and extends outward (Figs 2, 4; 13, 15; Yang states “the output electrode is connected to the lower arm copper layer” and the portion for connecting the external power source is located on the side of the power module near the lower arm chip unit).
Yang does not explicitly disclose a ceramic substrate, wherein an upper-layer copper sheet is arranged on an upper surface of the ceramic substrate, and the upper-layer copper sheet includes a first copper-sheet area, a second copper-sheet area, a negative- electrode copper-sheet area and a signal copper-sheet area that are not connected to each other; the second chipset is coupled to the negative-electrode copper-sheet area and the signal copper-sheet area through a second link device, and the second link device and the first link device are arranged in a laminated manner; and the negative electrode is coupled to the negative-electrode copper-sheet area and extends outward.
Yoshihara teaches a ceramic substrate (Fig 17; 9), wherein an upper-layer copper sheet is arranged on an upper surface of the ceramic substrate, and the upper-layer copper sheet includes a first copper-sheet area, a second copper-sheet area, a negative- electrode copper-sheet area and a signal copper-sheet area that are not connected to each other (Fig 17; 9, first copper sheet area 32 1, second copper sheet area 32 4, negative electrode copper sheet area 32 n, signal copper sheet area SL4; Yoshihara [0080, 0129]); the second chipset is coupled to the negative-electrode copper-sheet area and the signal copper-sheet area through a second link device (Fig 17; second chipset Q4, second link device 204/264, 32n,SL4; Yoshihara [0129-0130, 0137]), and the negative electrode is coupled to the negative-electrode copper-sheet area and extends outward (Fig 17, 19; N, 32n; Yoshihara [0117, 0129]).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Yang with a ceramic substrate, wherein an upper-layer copper sheet is arranged on an upper surface of the ceramic substrate, and the upper-layer copper sheet includes a first copper-sheet area, a second copper-sheet area, a negative- electrode copper-sheet area and a signal copper-sheet area that are not connected to each other; the second chipset is coupled to the negative-electrode copper-sheet area and the signal copper-sheet area through a second link device, and the negative electrode is coupled to the negative-electrode copper-sheet area and extends outward as taught by Yoshihara to get the benefit of simplifying the power module structure while permitting conduction of large current (Yoshihara [0092]).
Hao teaches the second link device and the first link device are arranged in a laminated manner (Figs 8-10; 512, 612; ; Hao states “he first main body part 612 is stacked on the second main body part 512”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Yang with the second link device and the first link device are arranged in a laminated manner as taught by Hao to get the benefit of reducing the parasitic inductance and resistance of the drive circuit.
Regarding Claim 3 – Yang in view of Yoshihara and Hao teaches the low-inductance current-sharing power module according to claim 1, wherein the first chipset arranged on the first copper-sheet area and the second chipset arranged on the second copper-sheet area are in bilateral symmetry with respect to the center line of the ceramic substrate (Yang Fig 3; 141/142, 151/152; Yang states the upper bridge arm chip unit and the lower bridge arm chip unit are “symmetrically disposed”).
Regarding Claim 5 – Yang in view of Yoshihara and Hao teaches the low-inductance current-sharing power module according to claim 1, wherein the first link device and the second link device are respectively coupled to the first chipset and the second chipset through metal blocks (Yoshihara Figs 15-17; 18, 201, 204, Q1, Q4; Yoshihara [0125. 0139] teaches metal stress relaxation layer 18 between the source leadframes and source pad electrodes).
Regarding Claim 6 – Yang in view of Yoshihara and Hao teaches the low-inductance current-sharing power module according to claim 1, wherein the first link device includes a first link body, a first link pin and first metal blocks of a number of p, and the first link body is respectively coupled top chips of the first chipset through the p first metal blocks, where p denotes a positive integer, the first link body is coupled to the second copper-sheet area through the first link pin (Yoshihara Fig 17; 201, 18, Q1, 324; Yoshihara [0116, 0129, 0139]).
Regarding Claim 8 – Yang in view of Yoshihara and Hao teaches the low-inductance current-sharing power module according to claim 1, wherein the first link device includes a first link body and a plurality of link pins, and a first end of each of the link pins is in connection with the first link body, a second end of each of p link pins is respectively coupled to p chips of the first chipset, and a second end of each of remaining link pins is coupled to the second copper-sheet area, where p denotes a positive integer (Yoshihara Fig 17; 201, Q1, 324; Yoshihara [0116, 0129]).
Regarding Claim 9 – Yang in view of Yoshihara and Hao teaches the low-inductance current-sharing power module according to claim 1, wherein the second link device includes a second link body and a plurality of link pins, a first end of each of the link pins is in connection with the second link body, a second end of each of q link pins is respectively coupled to q chips of the second chipset, and a second end of each of r link pins is coupled to the negative-electrode copper-sheet area, and a second end of each of the remaining link pins is coupled to the signal copper-sheet area, where q and r denote positive integers (Yoshihara Fig 17; 204/264, Q4, 32n, SL4; Yoshihara [0116, 0129-0130, 0137]).
Regarding Claim 10 – Yang in view of Yoshihara and Hao teaches the low-inductance current-sharing power module according to claim 1, wherein further comprising a G electrode and an S electrode, the G electrode and the S electrode are respectively in connection with different regions in the signal copper-sheet area and extend outward, wherein the S electrode is in connection with the second link device through the signal copper-sheet area (Yoshihara Figs 17, 19; GT4, SST4, GL4, SL4, 204/264; Yoshihara [0117, 0130, 0137]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (CN 109860160 A) in view of Yoshihara (US 20170092596 A1) and Hao et al. (CN 112510000 A) and in further view of Kato et al. (US 20210280549 A1) and Ichikawa (US 20210143093 A1)
Regarding Claim 4 – Yang in view of Yoshihara and Hao teaches the low-inductance current-sharing power module according to claim 1, wherein the negative electrode is arranged on the negative-electrode copper-sheet area (Yoshihara Fig 17; N, 32n; Yoshihara [0117, 0129]), but does not explicitly disclose two positive electrodes are respectively arranged on both protruded ends of the "concave"-shaped first copper-sheet area, and the two positive electrodes are symmetrical with respect to the negative electrode, and the output electrode is arranged on a central protruded part of the "convex"-shaped second copper-sheet area.
Kato teaches two positive electrodes are respectively arranged on both protruded ends of the "concave"-shaped first copper-sheet area, and the two positive electrodes are symmetrical with respect to the negative electrode (Figs 1, 5; 16a/16b, 17a, 23/25; Kato teaches the first conductive layer has a U-shape in planar view and the negative electrode terminal has a negative end portion disposed between the positive electrode ends).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Yang in view of Yoshihara and Hao with two positive electrodes are respectively arranged on both protruded ends of the "concave"-shaped first copper-sheet area, and the two positive electrodes are symmetrical with respect to the negative electrode as taught by Kato to get the benefit of reducing inductance between the PN terminals and reducing imbalance in switching timing.
Ichikawa teaches the output electrode is arranged on a central protruded part of the "convex"-shaped second copper-sheet area (Fig 1; 5a, 5b, 8d; Ichikawa [0016-0019]).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Yang in view of Yoshihara and Hao with the output electrode is arranged on a central protruded part of the "convex"-shaped second copper-sheet area as taught by Ichikawa to get the benefit of improving heat dissipation and balanced operation of the semiconductor chips.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (CN 109860160 A) in view of Yoshihara (US 20170092596 A1) and Hao et al. (CN 112510000 A) and in further view of Nikitin (US 20220005752 A1)
Regarding Claim 7 – Yang in view of Yoshihara and Hao teaches the low-inductance current-sharing power module according to claim 1, wherein the second link device includes a second link body, a second link pin, a third link pin and second metal blocks of a number of q, the second link body is respectively coupled to q chips of the second chipset through q second metal blocks, where q denotes a positive integer, the second link body is coupled to the negative-electrode copper-sheet area through the second link pin, and the second link body is coupled to the signal copper-sheet area through the third link pin (Yoshihara Fig 17; 204/264, 18, Q4, 32n, SL4 Yoshihara [0129-0130, 0137, 0139]).
Yang in view of Yoshihara and Hao does not explicitly disclose a thickness of the second metal block is greater than a thickness of the first metal block.
Nikitin teaches a thickness of the second metal block is greater than a thickness of the first metal block (Figs 2A-2D; 104’,104; Nikitin [0028] states “the inwardly positioned spacers 104′… may be thicker than the outwardly positioned spacers 104”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Yang in view of Yoshihara and Hao with a thickness of the second metal block is greater than a thickness of the first metal block as taught by Nikitin to get the benefit of accommodating different connection heights and semiconductor die thicknesses.
Allowable Subject Matter
Claim 2 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/ADITYA SHARMA/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
