ETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on October 18, 2024 has been considered by the Examiner.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-8, 10-12, 14-20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Oka et al (US 8,866,027; hereinafter Oka).
Regarding claim 1, Oka discloses a printed circuit board (PCB; 1), comprising: a metal substrate (2); an insulating layer (3) disposed on a side of the metal substrate (2), and provided with a through hole (6); a circuit layer (4) disposed on a side of the insulating layer (3) away from the metal substrate (2); a connector (7) disposed in the through hole (6) to electrically connect the metal substrate (2) and the circuit layer (4).
Regarding claim 2, Oka discloses the PCB (1), wherein the circuit layer (4) is provided with a first hole (see figure 4), the first hole (see figure 4) is communicated with the through hole (6), the connector (7) is disposed in the first hole, one end of the connector abuts against the metal substrate (2), and another end of the connector abuts against the circuit layer (4) to electrically connect the metal substrate and the circuit layer (see figure 5).
Regarding claim 3, Oka discloses the PCB (1), wherein the first hole (see figure 4) is a first blind hole, and an opening direction of the first blind hole is toward the insulating layer (3; see figure 4 or 5).
Regarding claim 4, Oka discloses the PCB (1), wherein the first hole is a first through hole (column 6 lines 48-51).
Regarding claim 6, Oka discloses the PCB (1), wherein the metal substrate (2) is provided with a second hole (column 6 lines 48-51), the second hole is communicated with the through hole, the connector (7) is disposed in the second hole, one end of the connector abuts against the metal substrate (2), and another end of the connector abuts against the circuit layer (4) to electrically connect the metal substrate and the circuit layer (see figure 5).
Regarding claim 7, Oka discloses the PCB (1), wherein the second hole (column 6 lines 48-51) is a second blind hole, and an opening direction of the second blind hole is toward the insulating layer (column 6 lines 48-51).
Regarding claim 8, Oka discloses the PCB (1), wherein the second hole is a second through hole (column 6 lines 48-51).
Regarding claim 10, Oka discloses the PCB (1),wherein the connector (7) is a metal rivet, the metal rivet (see figure 5) comprises a rivet head and a rivet rod, the metal rivet is disposed in the through hole (see figure 5), the rivet head abuts against the circuit layer, and the rivet rod abuts against the metal substrate to electrically connect the metal substrate and the circuit layer (see figure 5).
Regarding claim 11, Oka discloses the PCB (1), wherein a surface of the rivet head (see figure 5) abutting against the circuit layer (4) is an inclined surface, and a thickness of the rivet head gradually decreases from close to the rivet rod toward away from the rivet rod (see figure 5).
Regarding claim 12, Oka discloses the PCB (1), wherein a material of the connector (7) is the same as a material of the metal substrate (column 6 lines 4-6 and column 7 lines 4-9).
Regarding claim 14, Oka discloses a printed circuit board (PCB; 1) manufacturing method for manufacturing a PCB (1), comprising: providing a metal substrate (2); disposing an insulating layer (3) on the metal substrate (1), wherein the insulating layer (3) is provided with a through hole (6); disposing a connector in the through hole (6), wherein the connector (7) abuts against the metal substrate (2); disposing a circuit layer (4) on a side of the insulating layer (3) away from the metal substrate (2), wherein the circuit layer (4) abuts against the connector (7) such that the metal substrate (2) and the circuit layer (4) are electrically connected (see figures 5).
Regarding claim 15, Oka discloses the PCB manufacturing method (see figure 5), wherein the circuit layer (4) is provided with a first hole (6), the first hole (6) is communicated with the through hole, the connector (7) is disposed in the first hole (6), one end of the connector (7) abuts against the metal substrate (2), and another end of the connector (7) abuts against the circuit layer (4) to electrically connect the metal substrate and the circuit layer (see figure 5).
Regarding claim 16, Oka discloses the PCB manufacturing method (see figure 1), wherein the first hole (6) is a first blind hole, and an opening direction of the first blind hole is toward the insulating layer (see figure 5).
Regarding claim 17, Oka discloses the PCB manufacturing method (see figure 1), wherein the first hole (6) is a first through hole (column 6 lines 48-51).
Regarding claim 18, Oka discloses the PCB manufacturing method (see figure 1), wherein the metal substrate (2) is provided with a second hole (column 6 lines 48-51), the second hole is communicated with the through hole (6, see figure 5), the connector (7) is disposed in the second hole, one end of the connector (7) abuts against the metal substrate (2), and another end of the connector abuts against the circuit layer (4) to electrically connect the metal substrate (2) and the circuit layer (4).
Regarding claim 19, Oka discloses the PCB manufacturing method (see figure 1), wherein the second hole (column 6 lines 48-51) is a second blind hole, and an opening direction of the second blind hole is toward the insulating layer (3).
Regarding claim 20, Oka discloses a printed circuit board (PCB) manufacturing method for manufacturing a PCB (see figure 5), comprising: laminating a metal substrate (2), an insulating layer (3), and a circuit layer (4) in sequence to form a metal substrate (2) PCB; forming a through hole (6), wherein the through hole (6) at least extends through the insulating layer (3); disposing a connector (7) in the through hole (6), wherein the connector (7) abuts against the metal substrate (2) and the circuit layer (4) to electrically connect the metal substrate and the circuit layer (see figure 5).
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Oka et al (US 8,866,027; hereinafter Oka) in view of Palmeri et al (US 7,399,930; hereinafter Palmeri).
Regarding claim 5, Oka discloses the claimed invention except for a diameter of the first through hole is greater than a diameter of the through hole. Palmeri teaches a printed circuit board (302) having a first through hole (508,510) with a diameter greater than the diameter of a through hole (504; see figure 5). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make a diameter of the first through hole greater than a diameter of the through hole as taught by Palmeri to provide a countersink hole for a smooth surface connection. Furthermore, it has been held that such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Regarding claim 9, Oka discloses the claimed invention except for a diameter of the second through hole is greater than a diameter of the through hole. Palmeri teaches a printed circuit board (302) having a second through hole (508,510) with a diameter greater than the diameter of a through hole (504; see figure 5). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make a diameter of the second through hole greater than a diameter of the through hole as taught by Palmeri to provide a countersink hole for a smooth surface connection. Furthermore, it has been held that such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
4. Claims 13 is rejected under 35 U.S.C. 103 as being unpatentable over Oka et al (US 8,866,027; hereinafter Oka).
Regarding claim 13, Oka discloses the claimed invention except for the connector and the metal substrate are integrally formed. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to make the connector and the metal substrate integrally formed to save on manufacturing cost. Furthermore, it has been held that forming in one piece an article which has formerly been formed in two pieces and put together involves only routine skill in the art. In re Larson, 340 F.2d 965, 968, 144 USPQ 347, 349 (CCPA 1965).
Conclusion
5. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Nelson et al (US 12,200,853), Lu et al (US 11,785,707), Wang et al (US 11,589,458), Gomez (US 10,798,821), Lee et al (US 9,497,853), Watanabe et al (US 7,895,929) and Glovatsky et al (US 6,449,839) disclose a printed circuit board.
6. Any inquiry concerning this communication should be directed to Angel R. Estrada at telephone number (571) 272-1973. The Examiner can normally be reached on Monday-Friday (8:30am -5:00pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Imani N. Hayman can be reached on (571) 270-5528. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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June 25, 2026
/ANGEL R ESTRADA/Primary Examiner, Art Unit 2841
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