DETAILED ACTION
This is in response to the application filed on October 18, 2024 in which claims 1 – 17, 20, 32, and 33 are presented for examination (after preliminary amendment).
Status of Claims
Claims 1 – 17, 20, 32, and 33 are pending, of which claims 1, 17, and 33 are in independent form.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/18/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: DATA PROCESSING DEVICE, COPROCESSOR AND METHODS PERFORMED THEREBY FOR INTERRUPT HANDLING.
Drawings
The drawings are objected to because Figs. 6 – 8 show flowcharts with lines where arrows should be. The examiner recommends each flowchart box to output an arrow to show the flow. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 1 – 17, 20, 32, and 33 are objected to because of the following informalities: each independent claim states “a central processing unit, CPU.” The comma in this case causes doubt as to whether this is referring to a single CPU or two. The examiner recommends amending each independent claim 1, 17, and 33 to state “a central processing unit[[,]] (CPU).” All other claims inherit this objection based on their dependencies. Appropriate correction is required.
Claims 14 and 15 are objected to because of the following informalities: claims 14 and 15 introduce more acronyms separated by a comma. The examiner again recommends amending claims 14 and 15 to use parenthesis for acronyms. The examiner suggests amending claims 14 and 15 to state:
14. The data processing device according to claim 1,
wherein the predetermined task is associated with one of:
virtual router redundancy protocol[[,]] (VRRP);
bidirectional forwarding detection[[,]] (BFD);
operation, administration and maintenance[[,]] (OAM);
connectivity fault management[[,]] (CFM); and
memory error checking and correcting[[,]] (ECC).
15. The data processing device according to claim 1,
wherein the coprocessor is configured in one of:
a field programmable gate array[[,]] (FPGA);
a specific application integrated circuit[[,]] (ASIC);
a data processing unit[[,]] (DPU); and
an intelligence processing unit[[,]] (IPU).
Appropriate correction is required.
Claims 10 – 13 are objected to because of the following informalities: claim 10 includes “The data processing device (40) according to claim 1.” The examiner recommends amending claim 10 to state “The data processing device. Appropriate correction is required.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 5, 8, 15 – 17, 20, 32, and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Neiger et al., U.S. Patent Application 2023/0142399 (hereinafter referred to as Neiger) in view of Anand et al., U.S. Patent Application 2004/0186967 (hereinafter referred to as Anand).
Referring to claim 1, Neiger discloses “A data processing device comprising: a central processing unit, CPU; and a coprocessor configured to perform predetermined tasks for a plurality of sessions, and to report, for at least one session satisfying a predetermined condition, at least one interrupt event to the CPU” (Fig. 1 and [0033] processor 110 with one or more cores 115 and circuitry 120, circuitry 120 reports information from the interrupt expansion data structure to an interrupt handler. [0036] circuitry 120 may be integrated in a co-processor, “the circuitry 120 may include the core's circuitry that executes microcode to implement the functions of the circuitry 120.” [0060] and [0079] coprocessor including special purpose cores intended primarily for graphics and/or scientific); “wherein the coprocessor is configured to maintain: a bitmap table indicating, for each of the plurality of sessions, whether there is an interrupt event needing to be reported to the CPU” ([0034] additional information may correspond to a bitmap of multiple interrupts. [0037] circuitry determines if an interrupt vector associated with the interrupt corresponds to a data structure entry that is valid. [0041] bitmap and posted-interrupt descriptor (PID). [0042] each entry has a valid field. [0043] memory 520 stores interrupt expansion tables 525 and PIDs 527, bitmaps); “and wherein the CPU is configured to, in response to an interrupt signal triggered by the coprocessor, read, from the bitmap table, at least one row that as at least one interrupt event needing to be reported to the CPU” ([0032] “hardware interrupts may be posted into a data structure (e.g., a posted-interrupt data structure) such as a bitmap (e.g., with one bit per interrupt source). The bitmap may be contained in a posted-interrupt descriptor (PID). Embodiments of a processor include technology to report data from such a bitmap to the system software's interrupt handler.” [0037] the circuitry 335 may be configured to deliver an interrupt to the software interrupt handler based on an interrupt vector associated with the interrupt).
Neiger does not appear to explicitly disclose “row validity data indicating, for each of rows of the bitmap table, whether the row has at least one interrupt event needing to be reported to the CPU.” Also it follows that Neiger does not appear to explicitly disclose “and wherein the CPU is configured to, in response to an interrupt signal triggered by the coprocessor, read, from the bitmap table, at least one row that as at least one interrupt event needing to be reported to the CPU, according to the row validity data.”
However, Anand discloses another bitmap table (Fig. 2) including “row validity data indicating, for each of rows of the bitmap table, whether the row has at least one” high bit (Figure 2 261-266 and [0042] “the logical state "0" of the first block bit-flag 261 as the logical OR of the sixty-four segment bit-flags corresponding to the memory segments in the first memory block 221 (i.e., the sixty-four segment bit-flags shown in the first row of the segment bitmap 230). Similarly, one may view the logical state "1" of the fourth block bit-flag 264 as the logical OR of the sixty-four segment bit-flags corresponding to the memory segments in the fourth memory block 224 (i.e., the sixty-four segment bit-flags shown in the fourth row of the segment bitmap 230)”). Anand also discloses “read[ing], from the bitmap table, at least one row that as at least one” high bit, “according to the row validity data” ([0046] to efficiently identify a high bit, the circuitry may first identify a flag corresponding to a block of memory).
It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine the teachings of Anand’s block bit-flags with Neiger’s interrupt bitmap table so that the table includes “row validity data indicating, for each of rows of the bitmap table, whether the row has at least one interrupt event needing to be reported to the CPU.”
Neiger and Anand are analogous art because they are from the same field of endeavor, which is tables of data.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Neiger and Anand before him or her, to modify the teachings of Neiger to include the teachings of Anand so that the bitmap table includes row validity data indicating, for each of rows of the bitmap table, whether the row has at least one interrupt event needing to be reported to the CPU.
The motivation for doing so would have been to provide a means for quickly determining whether a row of the table includes any high bits (interrupts). The block bit flags of Anand save processing time of comparing each bit of a row, especially in the case of a row of all 0’s.
Therefore, it would have been obvious to combine Anand with Neiger to obtain the invention as specified in the instant claim.
As per claim 2, Neiger discloses “wherein the coprocessor comprises a memory configured to store the bitmap table” (Fig. 12 coprocessor memory 1334).
As per claim 3, Neiger/Anand discloses “wherein the coprocessor comprises a register configured to store the row validity data” (Neiger [0042] valid field is one bit. Anand [0090] flag in a register).
As per claim 4, Anand discloses “wherein the row validity data for a row of tl1e bitmap table is a result of an OR operation between bits of the row” ([0041] – [0042] “the logical state "0" of the first block bit-flag 261 as the logical OR of the sixty-four segment bit-flags corresponding to the memory segments in the first memory block 221 (i.e., the sixty-four segment bit-flags shown in the first row of the segment bitmap 230). Similarly, one may view the logical state "1" of the fourth block bit-flag 264 as the logical OR of the sixty-four segment bit-flags corresponding to the memory segments in the fourth memory block 224 (i.e., the sixty-four segment bit-flags shown in the fourth row of the segment bitmap 230)”).
As per claim 5, Neiger discloses “wherein the coprocessor is configured to operate in a first mode where the interrupt signal is triggered immediately after there is an interrupt event needing to be reported to the CPU” ([0002] interrupt requests processing in a timely manner).
As per claim 8, Neiger discloses “wherein the interrupt event comprises a first type of interrupt event and a second type of interrupt event; and wherein the coprocessor is configured to maintain, for each of the first type of interrupt event and the second type of interrupt event, a separate set of the bitmap table” ([0042] which type of PID" and "for every vector, they may be a set of PIDS").
Also, as above, Anand discloses “and the row validity data” (Figure 2 261-266 and [0042] “the logical state "0" of the first block bit-flag 261 as the logical OR of the sixty-four segment bit-flags corresponding to the memory segments in the first memory block 221 (i.e., the sixty-four segment bit-flags shown in the first row of the segment bitmap 230). Similarly, one may view the logical state "1" of the fourth block bit-flag 264 as the logical OR of the sixty-four segment bit-flags corresponding to the memory segments in the fourth memory block 224 (i.e., the sixty-four segment bit-flags shown in the fourth row of the segment bitmap 230)”). Anand also discloses “read[ing], from the bitmap table, at least one row that as at least one” high bit, “according to the row validity data” ([0046] to efficiently identify a high bit, the circuitry may first identify a flag corresponding to a block of memory).
It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine the teachings of Anand’s block bit-flags with Neiger’s interrupt bitmap table so that the table includes “row validity data indicating, for each of rows of the bitmap table, whether the row has at least one interrupt event needing to be reported to the CPU.”
Neiger and Anand are analogous art because they are from the same field of endeavor, which is tables of data.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Neiger and Anand before him or her, to modify the teachings of Neiger to include the teachings of Anand so that the bitmap table includes row validity data indicating, for each of rows of the bitmap table, whether the row has at least one interrupt event needing to be reported to the CPU.
The motivation for doing so would have been to provide a means for quickly determining whether a row of the table includes any high bits (interrupts). The block bit flags of Anand save processing time of comparing each bit of a row, especially in the case of a row of all 0’s.
Therefore, it would have been obvious to combine Anand with Neiger to obtain the invention as specified in the instant claim.
As per claim 15, Neiger discloses “wherein the coprocessor is configured in one of: a field programmable gate array, FPGA; a specific application integrated circuit, ASIC; a data processing unit, DPU; and an intelligence processing unit, IPU” ([0101] ASIC).
As per claim 16, Neiger discloses “wherein the data processing device is one of:
a communication device; and a network device” ([0065] a network or communication core and [0079] network or communication processor).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Neiger in view of Anand, as applied to claims above, further in view of Bajaj et al., U.S. Patent Application 2022/0200885 (hereinafter referred to as Bajaj).
As per claim 14, neither Neiger nor Anand appears to explicitly disclose “wherein the predetermined task is associated with one of: virtual router redundancy protocol, VRRP; bidirectional forwarding detection, BFD; operation, administration and maintenance, OAM; connectivity fault management, CFM; and memory error checking and correcting, ECC.”
However, Bajaj discloses another processor/co-processor system (Fig. 8 network node includes processor 810 and configuration monitor 806) dealing with interrupts ([0077] configuration monitor 806 generates alerts or interrupts) “wherein the predetermined task is associated with one of: virtual router redundancy protocol, VRRP; bidirectional forwarding detection, BFD; operation, administration and maintenance, OAM; connectivity fault management, CFM; and memory error checking and correcting, ECC” ([0067] and [0077] a configuration monitor 806 to monitor policy input as described above including BGP/OSPF updates, VRRP state updates, network interface state updates, and remote monitor updates, among others).
Neiger and Anand are analogous art because they are from the same field of endeavor, which is tables of data. Neiger and Bajaj are also analogous art because they are from the same field of endeavor, which is co-processors and interrupts.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Neiger, Anand, and Bajaj before him or her, to modify the teachings of Neiger and Anand to include the teachings of Bajaj so that the predetermined task is associated with virtual router redundancy protocol (VRRP).
The motivation for doing so would have been to provide a means for managing interrupts in a high availability network that can provide uninterrupted communication in the event of failure (as stated by Bajaj at [0003]).
Therefore, it would have been obvious to combine Bajaj with Neiger and Anand to obtain the invention as specified in the instant claim.
Allowable Subject Matter
Claims 6, 7, and 9 – 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Application 20030105798 and Patents 5727227, 7328294, 10664425 teach an interrupt coprocessor.
U.S. Patent 12379956 is the granted patent to Neiger.
U.S. Patents 11258700 and 11374849 are patents to Bajaj with similar teachings.
European Patent Application EP 2609595 B1 teaches a valid bit for each row of data.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN G SNYDER whose telephone number is (571)270-1971. The examiner can normally be reached on M-F 8:00am-4:30pm (flexible).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/STEVEN G SNYDER/Primary Examiner, Art Unit 2184