DETAILED ACTION
Claims 1-6 are pending in the present application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 12/11/2024 and 7/13/2026 were filed. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Yamada (JP 2002/151848 A, hereinafter Yamada) in view of Bhattacharyya et al. (“Nanoindentation Stress-Strain for Fracture Analysis and Computational Modeling for Hardness and Modulus”, JMEPEG (2018) 27:2719–2726, hereinafter Bhattacharyya).
Regarding claim 1, Yamada teaches a reliability test method for a printed wiring board substrate (see Abstract; see also translation page 6, para. 10 through page 7, para. 1, discussion of reliability test method for a printed wiring board substrate), the method comprising measuring conditions by which a crack occurs in the printed wiring board substrate (see translation page 6, para. 10 through page 7, para. 1, use of thermal cycling to determine when cracks occur described).
Yamada fails to specifically teach that the method comprising measuring a load at which a crack occurs in the printed wiring board substrate, using a nanoindenter.
Bhattacharyya teaches a method of measuring a load at which a crack occurs in a thin film coated Si substrate, using a nanoindenter (see Abstract; see also sections 2. Experimental, use of nanoindenter on Ti-B-Si-C and Si-C-N coatings on Si; see also Fig. 6, page 2721, para. 4, use of nanoindenter loading of the material to determine toughness (considered a factor of reliability) by loading the material until cracking occurs described).
Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art, to modify the method of Yamada such that the toughness of the printed wiring board substrate was determined utilizing a nanoindenter method as described by Bhattacharyya. This is because the use of nanoindentation has been a promising tool to determine harness and other mechanical properties at nanoscale as described by Bhattacharyya (see sections 1. Introduction).
Regarding claim 2, Yamada as modified by Bhattacharyya above teaches all of the limitations of claim 1.
Furthermore, Yamada teaches that the printed wiring board substrate includes a resin cured product and a glass cloth (see translation page 2, para. 3, discussion of printed wiring board substrate including resin cured glass cloth).
Regarding claim 4, Yamada as modified by Bhattacharyya above teaches all of the limitations of claims 1 and 2.
Yamada as modified by Bhattacharyya above fails to specifically teach that an indenter of the nanoindenter is pushed into the resin cured product.
However, as described above, Bhattacharyya teaches a method of measuring a load at which a crack occurs in a thin film coated Si substrate, using a nanoindenter (see Abstract; see also sections 2. Experimental, use of nanoindenter on Ti-B-Si-C and Si-C-N coatings on Si; see also Fig. 6, page 2721, para. 4, use of nanoindenter loading of the material to determine toughness (considered a factor of reliability) by loading the material until cracking occurs described).
Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art, to further modify the method of Yamada as modified by Bhattacharyya above such that the indenter was utilized to determine the toughness or reliability of the resin cured substrate in a manner as described by Bhattacharyya. This is because the use of nanoindentation has been a promising tool to determine harness and other mechanical properties at nanoscale as described by Bhattacharyya (see sections 1. Introduction).
Regarding claim 6, Yamada as modified by Bhattacharyya above teaches all of the limitations of claim 1.
Yamada as modified by Bhattacharyya above fails to specifically teach that a Berkovich indenter is used as an indenter of the nanoindenter.
However, Bhattacharyya further teaches that a Berkovich indenter is used as an indenter of the nanoindenter (see section 2. Experimental, para. 3, discussion of Berkovich indenter).
Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art, to further modify the method of Yamada as modified by Bhattacharyya above such that a Berkovich indenter was utilized as described by Bhattacharyya. This is because the use of a Berkovich nanoindentation has been a promising tool to determine harness and other mechanical properties at nanoscale as described by Bhattacharyya (see sections 1. Introduction).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yamada in view of Bhattacharyya as applied to claim 1, and further in view of Hirose (JP 2012-146990 A, hereinafter Hirose).
Regarding claim 3, Yamada as modified by Bhattacharyya above teaches all of the limitations of claim 1.
Yamada as modified by Bhattacharyya above fails to specifically teach that the printed wiring board substrate has two or more layers each including a resin cured product and a glass cloth.
Hirose teaches that it is known to form a printed wiring board substrate that utilizes two or more layers each including a resin cured product and a glass cloth (see Fig. 9; see also translation page 6, para. 2, use of multiple layers or resin cured glass cloth product within the multilayer printed wiring board substrate).
Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art, to modify the method of Yamada as modified by Bhattacharyya above such that the printed wiring board substrate included two or more layers each including resin cured produced and a glass cloth as suggested by Hirose. This allows for the formation of a multilayer circuit board having less warpage as suggested by Hirose (see Abstract).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Yamada in view of Bhattacharyya as applied to claim 1, and further in view of Sanchez et al. (“Cross-sectional Nanoindentation: A New Technique for Thin Film Interfacial Adhesion Characterization”, Acta mater. Vol. 47, No. 17, pp. 4405±4413, 1999, hereinafter Sanchez).
Regarding claim 5, Yamada as modified by Bhattacharyya above teaches all of the limitations of claim 1.
Yamada as modified by Bhattacharyya above fails to teach that an indenter of the nanoindenter is pushed into a cross sectional surface of the printed wiring board substrate.
Sanchez teaches method for characterizing the reliability of a cross sectional surface of a layered substrate utilizing a nanoindenter (see Abstract; see also Fig. 2 and section 2. Experimental Procedure, discussion of cross-sectional nanoindentation (CSN) method).
Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art, to modify the method of Yamada as modified by Bhattacharyya above such that the reliability of the printed wiring board substrate was tested utilizing cross-sectional nanoindentation as described by Sanchez. This allows for additional characterization of the material reliability by observation of interfacial cracking as described by Sanchez (see section 1. Introduction, para. 1).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHANIEL T WOODWARD whose telephone number is (571)270-0704. The examiner can normally be reached M-F: 9:00 AM - 5:00 PM.
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/NATHANIEL T WOODWARD/ Primary Examiner, Art Unit 2855
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