Prosecution Insights
Last updated: July 17, 2026
Application No. 18/860,690

WIRING BOARD STACKED BODY AND METHOD OF MANUFACTURING WIRING BOARD STACKED BODY

Non-Final OA §102
Filed
Oct 28, 2024
Priority
May 30, 2023 — nonprovisional of PCTJP2023020180
Examiner
BURNS, TREMESHA WILLIS
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Daiwa Co. Ltd.
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
9m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
673 granted / 867 resolved
+9.6% vs TC avg
Strong +18% interview lift
Without
With
+17.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
54 currently pending
Career history
887
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
47.2%
+7.2% vs TC avg
§102
49.9%
+9.9% vs TC avg
§112
1.8%
-38.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 867 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 – 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Igarashi et al. (U.S. Patent Publication No. 2013/0003314). Regarding claim 1, in Figures 5A – 5D, Igarashi discloses a wiring board stacked body comprising: a wiring board (10A, Figure 1A) having an opening (12); an embedded member (13) embedded in an inside of the opening formed in the wiring board; a hardened material (14A, 14B) containing a thermosetting resin (paragraph [0034]), disposed between the embedded member and an inner peripheral surface of the opening, and adhered to the wiring board (Figure 5D); and a wiring layer (20, 22) formed on surfaces of the wiring board, the embedded member and the thermosetting resin (Figure 5D), wherein the embedded member includes a ceramic body (paragraph [0046]), and metal films (15A, 15D) each formed on both surfaces of the ceramic body. Regarding claim 2, Igarashi discloses wherein a metal film non-formed region where the metal film is not formed is disposed on at least one surface of an outer edge portion of the embedded member, and the hardened material is disposed also between the ceramic body and the wiring layer in the metal film non-formed region (Figures 5A – 5D). Regarding claim 3, Igarashi discloses wherein the metal film non-formed region is formed on both surfaces of an outer edge portion of the embedded member, and the hardened material is also disposed between the ceramic body and the wiring layer in the both metal film non-formed regions of the ceramic body (Figures 5A – 5D). Regarding claim 4, Igarashi discloses wherein as viewed in a plan view, the metal film non-formed region is formed on the entirety of the outer edge portion so as to surround the metal film (Figures 5A – 5D). Regarding claim 5, Igarashi discloses wherein the metal film is formed on a surface of the ceramic body by plating using direct plating (Figures 5A – 5D). Regarding claim 6, Igarashi discloses wherein a metal layer is disposed on a surface of the wiring board, and a circuit wiring is constituted of the wiring layer, the metal layer and the metal film (Figures 5A – 5D). Regarding claim 7, Igarashi discloses wherein the metal layer is a metal plated film that is formed on a surface of the wiring board by plating (Figures 5A – 5D). Regarding claim 8, Igarashi discloses wherein the opening has a rectangular shape, and the embedded member has a rectangular shape as viewed in a plan view. Regarding claim 9, Igarashi discloses a method of manufacturing a wiring board stacked body for manufacturing the wiring board stacked body described in claim 1, the method comprising the steps of: obtaining a stacked body that includes: a wiring board or a wiring board material having an opening; an embedded member positioned in the opening; and a filling-use sheet or a hardened material of a coating layer containing a thermosetting resin that is integrated with the wiring board or the wiring board material, the thermosetting resin being filled between an inner surface of the opening formed in the wiring board or the wiring board material and the embedded member; and removing the hardened material by grinding the filing-use sheet or the cure material of the coating layer such that a thickness of the stacked body after grinding becomes a fixed value (Figures 5A – 5D). Regarding claim 10, Igarashi discloses the method of manufacturing a wiring board stacked body according to claim 9, further comprising the steps of: preparing a stacked material that includes the wiring board or the wiring board material, the embedded member, and the filling-use sheet; obtaining the stacked body by integrating the stacked material by heating and pressing, and removing a hardened material of the filling-use sheet by grinding the hardened material of the filling-use sheet such that a thickness of the stacked body before grinding becomes a fixed value (Figures 5A – 5D). Regarding claim 11, Igarashi discloses the method of manufacturing a wiring board stacked body according to claim 9, wherein the stacked body is a stacked body where a resin film having an opening at a position that corresponds to the opening formed in the wiring board or the wiring board material is adhered to the wiring board or the wiring board material, and the method further includes a step of setting a thickness of the stacked body after grinding to the thickness of the stacked body obtained by removing a portion of the resin film at a time of removing the hardened material of the filling-use sheet or the coating layer and, further, removing a remaining portion of the resin film from the stacked body; and a step of removing the hardened material of a thermosetting resin that covers the embedded member of the stacked body (Figures 5A – 5D). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. TREMESHA W. BURNS Primary Examiner Art Unit 2847 /TREMESHA W BURNS/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Oct 28, 2024
Application Filed
Jul 07, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
95%
With Interview (+17.7%)
2y 6m (~9m remaining)
Median Time to Grant
Low
PTA Risk
Based on 867 resolved cases by this examiner. Grant probability derived from career allowance rate.

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