Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
1. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
2. Claim 20 is rejected under 35 U.S.C. 101 because a computer-readable medium to store computer-readable code thereon would normally be considered statutory unless the specification defines “computer-readable medium” as including transient media such as signals, carrier waves, transmissions, optical waves, transmission media or other media incapable of being touched or perceived absent the non-transitory medium through which they are conveyed.
Claim 20 is not limited to non-transitory embodiments. Specifically, in view of the specification (¶0116) the computer readable medium is not limited to non-transitory embodiments, instead it has been defined/exemplified as including both non-transitory embodiments [e.g. removable storage drive, hard disk] and transitory embodiments [e.g. signals or transmission or carrier medium/media]. As such the claim is not limited to statutory subject matter and is therefore non statutory. Examiner suggests amending the claims using term "non-transitory computer readable medium".
Allowable Subject Matter
3. Claims 1-19 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Independent claims 1 and 19 refer to a processor interrupt controller comprising detection circuitry, a controller memory access circuitry, and control circuitry comprising a selected interrupt queue and a queue status summary structure. The controller detects an interrupt, and responsive to its identifier, controls signalling to a target handling context by controlling the memory access circuitry to issue write requests in accordance with a cache coherency protocol. The interrupt queue maintains interrupts according to their identifier to be processed by a target handling context, and the status summary structure indicates which queue holds pending interrupts that have yet to be processed by the handling context. The closest prior art of record are Yamashita (US 2013/0138850) and Shimizu (US 2007/0124523).
Yamashita and Shimizu, taken in combination, teach a processor interrupt controller comprising detection circuitry, a controller memory access circuitry, and control circuitry comprising interrupt queues including interrupt status indicators. The controller detects an interrupt, and responsive to its identifier, controls signalling to a target handling context by controlling the memory access circuitry to issue write requests in accordance with a cache coherency protocol. The interrupt queue maintains interrupts according to their identifier to be processed by a target handling context, and holds pending interrupts that have yet to be processed by the handling context.
Therefore, taken alone or in combination, fail to teach memory-based interrupt tracking structures including both interrupt queue structures to maintain pending interrupts for handling and a separate status summary structure to indicate which of the queued interrupts are awaiting processing by the appropriate handler, taken in combination with each other element of the claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bohizic (US 2008/0244570) discloses a processor for tracking the status of active interrupt queues.
Hofmann (US 2005/0210174) discloses a processor with an interrupt queue for handling accesses to memory.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J METZGER whose telephone number is (571)272-3105. The examiner can normally be reached Monday-Friday 8:30-5.
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/MICHAEL J METZGER/ Primary Examiner, Art Unit 2183