DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4, 5, 12-15, 19, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2023/0043951 A1 (Wang)
Wang discloses, referring primarily to figures 6-12, a circuit board, comprising: a base substrate (A101); and an electrical pattern (A400) disposed on the base substrate; the electrical pattern including a plurality of conductive patterns and a plurality of connection pads, a conductive pattern being electrically connected to at least one connection pad, and the connection pad being used to be connected to an electronic component (A600), wherein the electrical pattern is composed of at least one of a first conductive layer (A410) and a second conductive layer (A420, A430); the second conductive layer covers a surface of the first conductive layer away from the base substrate and two sides of the first conductive layer along an extension direction of the first conductive layer; the first conductive layer includes a first main material layer, a material of the first main material layer includes copper ([0127]), and the first main material layer is capable of forming a first intermetallic compound with solder; the electrical pattern includes: at least one of a first protective layer and a second protective layer (A430); the first protective layer is included in the first conductive layer, and the first protective layer is disposed on a side of the first main material layer away from the base substrate; the second protective layer (A430) is included in the second conductive layer; the first protective layer and the second protective layer are used to enhance oxidation resistance of the electrical pattern; and any of the first protective layer and the second protective layer is capable of forming a second intermetallic compound with the solder ([0127]) [claim 1], wherein the first conductive layer further includes: at least one additional layer disposed between the first main material layer and the base substrate, wherein the additional layer includes a second main material layer (A200) and a first stop layer (A440) that are stacked in a first direction; the first direction is a direction perpendicular to the base substrate and from the base substrate towards the first conductive layer; a material of the second main material layer includes copper ([0140]), and the second main material layer is capable of forming a first intermetallic compound with the solder; and the first stop layer is capable of forming a third intermetallic compound with the solder, and a reaction rate between the first stop layer and the solder is less than a reaction rate between the second main material layer and the solder ([0179]) [claim 2], wherein the second conductive layer includes a first covering area (d2) and a second covering area (d1-d2) that are connected; an orthographic projection of the first covering area on the base substrate covers an orthographic projection of the first conductive layer on the base substrate, and an orthographic projection of the second covering area on the base substrate is located on a side of the orthographic projection of the first conductive layer on the base substrate along the extension direction of the first conductive layer; and a distance between a side surface of the second covering area away from the first conductive layer and the first conductive layer is greater than or equal to 2 µm ([0185]) [claim 4], wherein the first conductive layer further includes an adhesive layer, and the adhesive layer is disposed on a side of the first main material conductive layer proximate to the base substrate; or the first conductive layer further includes an adhesive layer (A440), and the adhesive layer is disposed on a side of the first main material layer proximate to the base substrate; and a material of the adhesive layer includes any of molybdenum-nickel-titanium, molybdenum-niobium alloy, molybdenum, titanium, molybdenum-titanium alloy, molybdenum-tungsten alloy and molybdenum-tantalum alloy ([0179]) [claim 5], further comprising a reverse stress layer (A300) located between the base substrate and the first conductive layer, wherein a material of the reverse stress layer includes any of silicon nitride and silicon oxide ([0158]-[0159]) [claim 12], wherein the circuit board has a plurality of edges; the circuit board has a device area and at least one bonding area, and the bonding area is closer to any edge of the circuit board than the device area; and the plurality of connection pads are divided into a plurality of device connection pads and a plurality of chip connection pads; and the plurality of device connection pads are located in the device area, and the plurality of chip connection pads are located in the bonding area (best seen in figure 15) [claim 13].
Additionally, Wang discloses a light-emitting substrate, comprising the circuit board according to claim 1 (as described above); and further comprising: an electronic component (A600), wherein pins of the electronic component are electrically connected to connection pads of the circuit board by solder (A700) [claim 15].
Furthermore, Wang discloses a display panel ([0005]), comprising the light-emitting substrate according to claim 15 (as described above) [claim 19].
Moreover, Wang discloses a display apparatus ([0005]), comprising the display panel according to claim 19 (as described above) [claim 20].
Also, regarding claim 14, Wang discloses, a method for manufacturing a circuit board, comprising: providing a base substrate (A101); forming a first initial conductive layer (A200) on a side of the base substrate; the first initial conductive layer including a first initial main material layer (A200) and/or a first initial protective layer (A300); forming a first conductive layer, including: forming the first conductive layer from the first initial conductive layer using a single patterning process; wherein the first initial main material layer forms a first main material layer, and the first initial protective layer forms a first protective layer; and/or forming a second initial conductive layer (A400) on a side of the first conductive layer away from the base substrate; the second initial conductive layer including a second initial protective layer; and forming a second conductive layer, including: form the second conductive layer from the second initial conductive layer using a single patterning process; wherein the second initial protective layer forms a second protective layer [claim 14].
Allowable Subject Matter
Claims 3, 7-11, 16-18, and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claim 3 states the limitation “the second stop layer is capable of forming a fourth intermetallic compound with the solder, and a reaction rate between the second stop layer and the solder is less than a reaction rate between the third main material layer and the solder.” This limitation, in conjunction with the other claimed features, was neither found to be disclosed in, nor suggested by the prior art. Claims 7-9 state the limitation “the second conductive layer further includes a second stop layer a material of the first protective layer, a material of the second protective layer, a material of the first stop layer, a material of the second stop layer and a material of the adhesive layer each include any of nickel and nickel alloys.” This limitation, in conjunction with the other claimed features, was neither found to be disclosed in, nor suggested by the prior art. Claim 10 states the limitation “a sum of dimensions of the first stop layer, the second stop layer, the adhesive layer, the first protective layer and the second protective layer in the first direction is in a range of 0.02 µm to 2 µm, inclusive; and a dimension of any of the first stop layer, the second stop layer, the adhesive layer, the first protective layer and the second protective layer in the first direction is in a range of 100 A to 10000 A, inclusive; or in a case where the material of the adhesive layer includes any of molybdenum-nickel- titanium alloy, molybdenum-niobium alloy, molybdenum, titanium, molybdenum-titanium alloy, molybdenum-tungsten alloy and molybdenum-tantalum alloy, a dimension of the adhesive layer in the first direction is in a range of 200 A to 1000 A, inclusive; wherein the first direction is a direction perpendicular to the base substrate and from the base substrate towards the first conductive layer.” This limitation, in conjunction with the other claimed features, was neither found to be disclosed in, nor suggested by the prior art. Claim 11 states the limitation “a dimension of the seed layer in the first direction is in a range of 1000 A to 9000 A, inclusive; and a dimension of the growth layer in the first direction is in a range of 2 µm to 15 µm, inclusive.” This limitation, in conjunction with the other claimed features, was neither found to be disclosed in, nor suggested by the prior art. Claim 16 states the limitation “further comprising: a reflective layer, wherein the reflective layer is disposed on a side of the electrical pattern away from the base substrate; the reflective layer is provided with a plurality of openings therein, and the pins of the electronic component are electrically connected to the solder and the connection pads through openings.” This limitation, in conjunction with the other claimed features, was neither found to be disclosed in, nor suggested by the prior art. Claims 17 and 18 state the limitation “wherein the light-emitting substrate has a light-exit side and a non-light-exit side that are opposite; and a plurality of optical films disposed on the light-exit side of the light-emitting substrate.” This limitation, in conjunction with the other claimed features, was neither found to be disclosed in, nor suggested by the prior art. Claim 21 states the limitation “a sum of dimensions of the first stop layer, the second stop layer, the adhesive layer, the first protective layer and the second protective layer in a first direction is in a range of 0.02 µm to 2 µm, inclusive; and a dimension of any of the first stop layer, the second stop layer, the adhesive layer, the first protective layer and the second protective layer in the first direction is in a range of 100 A to 10000 A, inclusive; or the first conductive layer further includes an adhesive layer, and the material of the adhesive layer includes any of molybdenum-nickel-titanium alloy, molybdenum-niobium alloy, molybdenum, titanium, molybdenum-titanium alloy, molybdenum-tungsten alloy and molybdenum-tantalum alloy; a dimension of the adhesive layer in the first direction is in a range of 200 A to 1000 A, inclusive; wherein the first direction is a direction perpendicular to the base substrate and from the base substrate towards the first conductive layer.” This limitation, in conjunction with the other claimed features, was neither found to be disclosed in, nor suggested by the prior art.
Conclusion
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JEREMY C. NORRIS
Examiner
Art Unit 2847
/JEREMY C NORRIS/Primary Examiner, Art Unit 2847
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