DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR TRANSISTOR DEVICE WITH STACKED METAL OXIDE LAYERS IN AN OPENING BETWEEN MULTIPLE ELECTRODES
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of copending Application No. 18/729,577 in view of Jin et al. CN 112750913 A, hereinafter “Jin”. This is a provisional nonstatutory double patenting rejection.
18/864,123 Instant claim 1
(Currently Amended) A semiconductor device comprising:
a first conductive layer (Ref. first conductive layer):
a first insulating layer comprising a first opening reaching the first conductive, layer (Ref second insulating layer with opening):
a second conductive layer over the first insulating layer and comprising a second opening overlapping with the first opening (Ref second conductive layer with second opening),
a first oxide semiconductor layer (Ref semiconductor layer) [[is]] in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, and a top surface and a side surface of the second conductive layer (same structure is claimed in Ref):
a second oxide semiconductor layer over the first oxide semiconductor layer (Ref does not claim second oxide semiconductor layer, but it is obvious in view of Jin):
a second insulating layer (Ref third insulating layer) over the second oxide semiconductor, layer;
and a third conductive layer (Ref third conductive layer) overlapping with the first oxide semiconductor layer and the second oxide semiconductor layer with the second insulating layer therebetween,
[[and]] wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises a region embedded in the first opening and the second opening (Ref does not claim second oxide semiconductor),
and wherein a conductivity of the first oxide semiconductor layer is higher than a conductivity of the second oxide semiconductor layer (Ref does not claim conductivity of semiconductor layer).
18/729,577 Reference claim 1
A display apparatus comprising : a transistor, a light-emitting device,
and a first insulating layer, wherein the transistor comprises a semiconductor layer,
a first conductive layer, a second conductive layer, a third conductive layer, a second insulating layer, and a third insulating layer,
wherein the second insulating layer is provided over the first conductive layer,
wherein the second insulating layer comprises a first opening reaching the first conductive layer,
wherein the second conductive layer is provided over the second insulating layer,
wherein the second conductive layer comprises a second opening in a region overlapping with the first opening,
wherein the semiconductor layer is in contact with a top surface of the first conductive layer, a side surface of the second insulating layer, and a top surface and a side surface of the second conductive layer,
wherein the third insulating layer is provided over the semiconductor layer,
wherein the third conductive layer is provided over the third insulating layer,
wherein the first insulating layer is provided over the transistor,
wherein the first insulating layer and the third insulating layer comprise a third opening reaching the second conductive layer,
…..
Copending application 18/729,577 does not claim the second oxide semiconductor layer wherein the conductivity of the first oxide semiconductor layer is higher than a conductivity of the second oxide semiconductor layer.
However, in the same field of endeavor of creating highly efficient display devices with oxide channel layers [Jin 0002-0004], Jin discloses a thin film transistor suitable for use in transparent display devices [Jin 0096] comprising stacked oxide semiconductor layer (Jin Fig 17E layers 131 and 132) a second oxide semiconductor layer over the first oxide semiconductor layer (Jin Fig 17E layer 132 over layer 131), wherein a conductivity of the first oxide semiconductor (layer 131) is higher than a conductivity of the second oxide semiconductor layer (“layer 132 may have a lower conductivity and a wider band gap than the first oxide semiconductor layer 131” [Jin 0107]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the single oxide semiconductor layer disclosed in Kimura with the stacked first and second oxide semiconductor layer that is clearly disclosed in Jin “to achieve a short channel while maintaining threshold voltage value and an NBTIS characteristic, thereby improving the reliability of the thin film transistor” [Jin 0099].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kimura et al. WO 2023/203429 A1 (eligible as prior art under 102(a)(2) with a foreign priority date to Japan in April 22, 2022), hereinafter “Kimura” in view of Jin et al. CN 112750913 A, hereinafter “Jin”.
Regarding independent claim 1, Kimura discloses A semiconductor device (Kimura: transistor 33, Fig 3A) comprising:
a first conductive layer:(Fig 3A, conductive layer 111)
a first insulating layer comprising a first opening reaching the first conductive layer (insulating layer 103, with opening shown in Fig 3, opening 121 [0175])
a second conductive layer over the first insulating layer and comprising a second opening overlapping with the first opening (second conductive layer 112a-b, the opening of the second conductor overlaps the opening 121 [0176]),
a first oxide semiconductor layer (the metal oxide semiconductor layer 113 [0228]) [[is]] in contact with a top surface of the first conductive layer (Fig 3A, 113 contacts top of 111), a side surface of the first insulating layer (113 contacts the sides of 103), and a top surface and a side surface of the second conductive layer (113 is disposed on the top of 112a-b and touches the inner sides of both second conductive layers):
Kimura does not explicitly disclose: a second oxide semiconductor layer over the first oxide semiconductor layer: a second insulating layer over the second oxide semiconductor, layer; and a third conductive layer overlapping with the first oxide semiconductor layer and the second oxide semiconductor layer with the second insulating layer therebetween, [[and]] wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises a region embedded in the first opening and the second opening, and wherein a conductivity of the first oxide semiconductor layer is higher than a conductivity of the second oxide semiconductor layer.
However, in the same field of endeavor of creating highly efficient display devices with oxide channel layers [Jin 0002-0004], Jin discloses a thin film transistor suitable for use in transparent display devices [Jin 0096] comprising stacked oxide semiconductor layer. Jin Fig 17E discloses a second oxide semiconductor layer (second oxide semiconductor layer 132 Jin Fig 17E) over the first oxide semiconductor layer (first oxide semiconductor layer 131); wherein a conductivity of the first oxide semiconductor layer is higher than a conductivity of the second oxide semiconductor layer (Jin [0107] “the second oxide semiconductor layer 132 may have a lower conductivity and a wider band gap than the first oxide semiconductor layer 121”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the single oxide semiconductor layer disclosed in Kimura with the stacked first and second oxide semiconductor layer that is clearly disclosed in Jin “to achieve a short channel while maintaining threshold voltage value and an NBTIS characteristic, thereby improving the reliability of the thin film transistor” [Jin 0099].
The modification of Kimura with the stacked oxides as disclosed in Jin results in the final limitations of claim 1: a second oxide semiconductor layer (Kimura modified to have the first and second oxide semiconductor layers of Jin Fig 17E, 131 and 132, respectively) over the first oxide semiconductor layer (Jin Fig 17E 132 is stacked over 131): a second insulating layer (Kimura Fig 3A second insulating layer 105) over the second oxide semiconductor layer (105 sits over Kimura’s semiconductor oxide layer, which can be obviously modified and substituted with Jin’s first and second semiconductor oxides); and a third conductive layer (Kimura Fig 3A gate electrode layer 115) overlapping with the first oxide semiconductor layer and the second oxide semiconductor layer with the second insulating layer therebetween (115 overlaps 113, 111, and 103 with 105 in between in Kimura Fig 3A), [[and]] wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises a region embedded in the first opening and the second opening (modified Kimura has both oxide semiconductor layers in the opening 121 shown in Kimura Figs 3-3A).
Claim 2 is cancelled in the amended claims filed May 12, 2025.
Regarding claim 3, Kimura in view of Jin discloses The [[A]] semiconductor device according to claim 1 (Kimura’s structure with the substitution of Jin’s stacked oxide semiconductor layers), wherein the first oxide semiconductor layer (Jin Fig 17E 131) comprises a first metal oxide (Jin 131 is made of iron-indium-zinc oxide (FIZO) [abstract]), wherein the second oxide semiconductor layer (Jin Fig 17E 132) comprises a second metal oxide (132 made of indium-gallium-zinc oxide (IGZO) [abstract]), and wherein a band gap of the first metal oxide is smaller than a band gap of the second metal oxide (“the bad gap energy of the second oxide semiconductor layer can be in the range of 105% to 130% of the band gap energy of the first oxide semiconductor layer” [Jin 0016]) .
Regarding claim 4, Kimura in view of Jin discloses The [[A]] semiconductor device according to The [[A]] semiconductor device according to claim 1 (Kimura modified with the stacked oxide semiconductor layers of Jin) wherein the first oxide semiconductor layer comprises a first metal oxide (Jin [abstract] “first oxide semiconductor layer formed by iron-indium-zinc oxide (FIZO) and a second oxide semiconductor layer formed by indium-gallium-zinc oxide (IGZO)”) , wherein the second oxide semiconductor layer comprises a second metal oxide (the second metal oxide comprises a different metal oxide than the first metal oxide)
wherein the first metal oxide comprises indium (Jin [abstract] the first oxide semiconductor layer 131 in Fig 17E comprises indium) wherein the second metal oxide comprises indium and an element M (the second oxide semiconductor layer 132 comprises indium and gallium Jin [abstract]),
wherein the element M is one or more of gallium, aluminum, and tin (M is gallium) and wherein a content percentage of the element M in the first metal oxide is lower than a content percentage of the element M in the second metal oxide (the layer 131 in Jin Fig 17E does not contain gallium, so the content percentage of gallium in the second oxide, layer 132, is higher than that of the first oxide, layer 131).
Claim 5 is cancelled in the amended claims filed May 12, 2025.
Regarding claim 6, Kimura in view of Jin discloses (Currently Amended) The semiconductor device according to claim 1, wherein the first conductive layer (Kimura Fig 3A 111) and the second conductive layer (112a and 112b) each comprise an oxide conductor (Kimura "a metal oxide film (also referred to as an oxide conductor) can be used for the conductive layer 111, the conductor layer 112a, and conductive layer 112b, and the conductive layer 115" [Kimura 0214].
Claim(s) 1-9 are further rejected under 35 U.S.C. 103 as being unpatentable over Sasaki et al. US 2017/0271375 A1, hereinafter “Sasaki”, in view of Jin et al. CN 112750913 A, hereinafter “Jin”.
Regarding independent claim 1, Sasaki discloses A semiconductor device (Sasaki Fig 129 first transistor 20, [Page 130 out of 380]) comprising:
a first conductive layer (Fig 129 lower electrode 120M)
a first insulating layer comprising a first opening reaching the first conductive layer (opening 139M inside of insulating layer 130M Fig 129)
a second conductive layer over the first insulating layer and comprising a second opening overlapping with the first opening (upper electrode 140M, with same opening in opening 139M))
a first oxide semiconductor layer (oxide semiconductor layer 160M) [[is]] in contact with a top surface of the first conductive layer (160M contacts top of 120M), a side surface of the first insulating layer (160M contacts sides of 130M), and a top surface and a side surface of the second conductive layer (160M sits on top of 140M and contacts the side surfaces in the opening 139M):
Sasaki does not explicitly disclose: a second oxide semiconductor layer over the first oxide semiconductor layer: a second insulating layer over the second oxide semiconductor, layer; and a third conductive layer overlapping with the first oxide semiconductor layer and the second oxide semiconductor layer with the second insulating layer therebetween, [[and]] wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises a region embedded in the first opening and the second opening, and wherein a conductivity of the first oxide semiconductor layer is higher than a conductivity of the second oxide semiconductor layer.
However, in the same field of endeavor of creating highly efficient display devices with oxide channel layers [Jin 0002-0004], Jin discloses a thin film transistor suitable for use in transparent display devices [Jin 0096] comprising stacked oxide semiconductor layer. Jin Fig 17E discloses a second oxide semiconductor layer (second oxide semiconductor layer 132 Jin Fig 17E) over the first oxide semiconductor layer (first oxide semiconductor layer 131); wherein a conductivity of the first oxide semiconductor layer is higher than a conductivity of the second oxide semiconductor layer (Jin [0107] “the second oxide semiconductor layer 132 may have a lower conductivity and a wider band gap than the first oxide semiconductor layer 121”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the single oxide semiconductor layer disclosed in Sasaki with the stacked first and second oxide semiconductor layer that is clearly disclosed in Jin “to achieve a short channel while maintaining threshold voltage value and an NBTIS characteristic, thereby improving the reliability of the thin film transistor” [Jin 0099].
The modification of Sasaki Fig 129 with the stacked oxides as disclosed in Jin results in the final limitations of claim 1: a second oxide semiconductor layer (Sasaki modified to have the first and second oxide semiconductor layers of Jin Fig 17E, 131 and 132, respectively) over the first oxide semiconductor layer (Jin Fig 17E 132 is stacked over 131): a second insulating layer (Sasaki Fig 129 gate insulating layer 170M) over the second oxide semiconductor layer (170M is disposed over 160M in Sasaki Fig 129); and a third conductive layer (Fig 129 gate electrode 180M) overlapping with the first oxide semiconductor layer and the second oxide semiconductor layer with the second insulating layer therebetween (180M overlaps 160M, and 170M), [[and]] wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises a region embedded in the first opening and the second opening (modified Sasaki has both oxide semiconductor layers in the opening 139M shown in Sasaki Fig 129).
Claim 2 is cancelled in the amended claims filed May 12, 2025.
Regarding claim 3, Sasaki in view of Jin discloses The [[A]] semiconductor device according to claim 1 (Sasaki’s Fig 129 structure with the substitution of Jin’s stacked oxide semiconductor layers), wherein the first oxide semiconductor layer (Jin Fig 17E 131) comprises a first metal oxide (Jin 131 is made of iron-indium-zinc oxide (FIZO) [abstract]), wherein the second oxide semiconductor layer (Jin Fig 17E 132) comprises a second metal oxide (132 made of indium-gallium-zinc oxide (IGZO) [abstract]), and wherein a band gap of the first metal oxide is smaller than a band gap of the second metal oxide (“the bad gap energy of the second oxide semiconductor layer can be in the range of 105% to 130% of the band gap energy of the first oxide semiconductor layer” [Jin 0016]) .
Regarding claim 4, Sasaki in view of Jin discloses The [[A]] semiconductor device according to The [[A]] semiconductor device according to claim 1 (Sasaki modified with the stacked oxide semiconductor layers of Jin) wherein the first oxide semiconductor layer comprises a first metal oxide (Jin [abstract] “first oxide semiconductor layer formed by iron-indium-zinc oxide (FIZO) and a second oxide semiconductor layer formed by indium-gallium-zinc oxide (IGZO)”) , wherein the second oxide semiconductor layer comprises a second metal oxide (the second metal oxide comprises gallium)
wherein the first metal oxide comprises indium (Jin [abstract] the first oxide semiconductor layer 131 in Fig 17E comprises indium) wherein the second metal oxide comprises indium and an element M (the second oxide semiconductor layer 132 comprises indium and gallium Jin [abstract]),
wherein the element M is one or more of gallium, aluminum, and tin (M is gallium)and wherein a content percentage of the element M in the first metal oxide is lower than a content percentage of the element M in the second metal oxide (the layer 131 in Jin Fig 17E does not explicitly contain gallium, so the content percentage of gallium in the second oxide, layer 132, is higher than that of the first oxide, layer 131).
Claim 5 is cancelled in the amended claims filed May 12, 2025.
Regarding claim 6, Sasaki in view of Jin discloses (Currently Amended) The semiconductor device according to claim 1, wherein the first conductive layer (Saski Fig 129 lower electrode 120M) and the second conductive layer (140M) each comprise an oxide conductor (“for the lower electrode 120 and the upper electrode 140, a general metal material or a conductive semiconductor material can be used …. Further a conductive oxide semiconductor, …, can be used” [Sasaki 0031]).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kimura in view of Jin as applied to claim 1, further in view of Yamazaki et al. US 2022/0223721 A1, hereinafter “Yama”.
Regarding claim 7, Kimura in view of Jin discloses The semiconductor device according to claim 1, but Kimura and Jin both fail to disclose wherein the first insulating layer comprises a third insulating layer, a fourth insulating layer over the third insulating layer, and a fifth insulating layer over the fourth insulating layer, wherein the fourth insulating layer comprises oxygen, and wherein the third insulating layer and the fifth insulating layer each comprise nitrogen.
However, in the same field of endeavor, Yama discloses a semiconductor device which comprises a first insulating layer made of stacked layers. Yama Fig 6B discloses the first insulating layer (all three layers 212, 214, and 216 Yama Fig 6B) comprises a third insulating layer (let 212 be the third insulating layer), a fourth insulating layer (let 214 be the fourth insulating layer) over the third insulating layer, and a fifth insulating layer (let 216 be the fifth insulating layer) over the fourth insulating layer, wherein the fourth insulating layer comprises oxygen (“for the insulator 214, aluminum oxide is deposited by a sputtering method” [Yama 0300]) , and wherein the third insulating layer and the fifth insulating layer each comprise nitrogen (silicon nitride is preferably used for layer 212 [Yama 0519] and “silicon oxide or silicon oxynitride is used as the insulator 216” [Yama 0302]).
Therefore, it would have been obvious to one having ordinary skill in the art to replace the single insulator layer as disclosed in Kimura Fig 3A with the multi-stack of oxygen and nitrogen-containing insulating materials serves the purpose of “inhibiting passage of oxygen and impurities such as hydrogen” [Yama 0506].
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki in view of Jin as applied to claim 1, further in view of Yama.
Regarding claim 7, Saski in view of Jin discloses The semiconductor device according to claim 1, but Sasaki and Jin both fail to disclose wherein the first insulating layer comprises a third insulating layer, a fourth insulating layer over the third insulating layer, and a fifth insulating layer over the fourth insulating layer, wherein the fourth insulating layer comprises oxygen, and wherein the third insulating layer and the fifth insulating layer each comprise nitrogen.
However, in the same field of endeavor, Yama discloses a semiconductor device which comprises a first insulating layer made of stacked layers. Yama Fig 6B discloses the first insulating layer (all three layers 212, 214, and 216 Yama Fig 6B) comprises a third insulating layer (let 212 be the third insulating layer), a fourth insulating layer (let 214 be the fourth insulating layer) over the third insulating layer, and a fifth insulating layer (let 216 be the fifth insulating layer) over the fourth insulating layer, wherein the fourth insulating layer comprises oxygen (“for the insulator 214, aluminum oxide is deposited by a sputtering method” [Yama 0300]) , and wherein the third insulating layer and the fifth insulating layer each comprise nitrogen (silicon nitride is preferably used for layer 212 [Yama 0519] and “silicon oxide or silicon oxynitride is used as the insulator 216” [Yama 0302]).
Therefore, it would have been obvious to one having ordinary skill in the art to replace the single insulator layer as disclosed in Sasaki Fig 129 with the multi-stack of oxygen and nitrogen-containing insulating materials serves the purpose of “inhibiting passage of oxygen and impurities such as hydrogen” [Yama 0506].
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kimura in view of Jin as applied to claim 1, further in view of Kanagawa et al. CN 113906570 A, hereinafter “Kanagawa”.
Regarding claim 8, Kimura in view of Jin discloses The semiconductor device according to claim 1, but Kimura and Jin both fail to disclose an embodiment wherein the first insulating layer (Kimura Fig 3A 103) comprises a third insulating layer, a fourth insulating layer over the third insulating layer, a fifth insulating layer over the fourth insulating layer, and a sixth insulating layer over the fifth insulating layer, wherein the fifth insulating layer comprises oxygen, wherein the third insulating layer, the fourth insulating layer, and the sixth insulating layer each comprise nitrogen, and wherein the third insulating layer comprises a region having a higher hydrogen content than the fourth insulating layer.
However, in the same field of endeavor, Kanagawa discloses, in Fig 38B, a device comprising stacked insulating layers 212, 214, 222, 224 where the materials may be aluminum oxide (AlO), silicon nitride (SiN), silicon oxynitride (SiON), etc. The order of the stacked materials in Kanagawa is disclosed to preferably be SiN [0332], SiN [0430], AlO [0346], and SiON [0349], respectively. This stack of insulating layers may make up one overall first insulating layer; thereby, disclosing wherein the first insulating layer (Kanagawa Fig 38B insulating layers 214-224) comprises a third insulating layer (212), a fourth insulating layer (214) over the third insulating layer, a fifth insulating layer (222) over the fourth insulating layer, and a sixth insulating (224) layer over the fifth insulating layer, wherein the fifth insulating layer comprises oxygen (layer 222 preferably contains AlO [Kanagawa 0346]), wherein the third insulating layer, the fourth insulating layer, and the sixth insulating layer each comprise nitrogen (layers 212, 214, and 224 may each comprise SiON or SiN [Kanagawa 0332, 0430, 0349]), and wherein the third insulating layer (Fig 38B 212) comprises a region having a higher hydrogen content than the fourth insulating layer (“the hydrogen concentration of the insulator 214 is preferably lower than the hydrogen concentration of the insulator 212” [0427]; therefore, the third layer 212 has a region having a higher hydrogen concentration than the fourth layer 214).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of the device as disclosed in Kimura and Jin to substitute the single insulating layer (Kimura Fig 3A 103) with the stacked insulating layers as disclosed in Kanagawa Fig 38B with the a stack of insulators having specific nitrogen and oxygen materials to “inhibit hydrogen and other impurities diffused to the inner side of the transistor 200” [Kanagawa 0346].
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki in view of Jin as applied to claim 1, further in view of Kanagawa et al. CN 113906570 A, hereinafter “Kanagawa”.
Regarding claim 8, Sasaki in view of Jin discloses The semiconductor device according to claim 1, but Sasaki and Jin both fail to disclose an embodiment wherein the first insulating layer comprises a third insulating layer, a fourth insulating layer over the third insulating layer, a fifth insulating layer over the fourth insulating layer, and a sixth insulating layer over the fifth insulating layer, wherein the fifth insulating layer comprises oxygen, wherein the third insulating layer, the fourth insulating layer, and the sixth insulating layer each comprise nitrogen, and wherein the third insulating layer comprises a region having a higher hydrogen content than the fourth insulating layer.
However, in the same field of endeavor, Kanagawa discloses, in Fig 38B, a device comprising stacked insulating layers 212, 214, 222, 224 where the materials may be aluminum oxide (AlO), silicon nitride (SiN), silicon oxynitride (SiON), etc. The order of the stacked materials in Iida is disclosed to preferably be SiN [0332], SiN [0430], AlO [0346], and SiON [0349], respectively. This stack of insulating layers may make up one overall first insulating layer; thereby, disclosing wherein the first insulating layer (Kanagawa Fig 38Binsulating layers 214-224) comprises a third insulating layer (212), a fourth insulating layer (214) over the third insulating layer, a fifth insulating layer (222) over the fourth insulating layer, and a sixth insulating (224) layer over the fifth insulating layer, wherein the fifth insulating layer comprises oxygen (layer 222 preferably contains AlO [Kanagawa 0346]), wherein the third insulating layer, the fourth insulating layer, and the sixth insulating layer each comprise nitrogen (layers 212, 214, and 224 may each comprise SiON or SiN [Kanagawa 0332, 0430, 0349]), and wherein the third insulating layer (Fig 38B 212) comprises a region having a higher hydrogen content than the fourth insulating layer (“the hydrogen centration of the insulator 214 is preferably lower than the hydrogen concentration of the insulator 212” [0427]; therefore, the third layer 212 has a region having a higher hydrogen concentration than the fourth layer 214).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of the device as disclosed in Sasaki and Jin to substitute the single insulating layer (Sasaki Fig 129) with the stacked insulating layers as disclosed in Kanagawa Fig 38B with the a stack of insulators having specific nitrogen and oxygen materials to “inhibit hydrogen and other impurities diffused to the inner side of the transistor 200” [Kanagawa 0346].
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kimura in view of Jin as applied to claim 1, further in view of Yamazaki et al. US 2022/0139917 A1 hereinafter “Yama2”.
Regarding claim 9, Kimura in view of Jin discloses The semiconductor device according to claim 1, (Kimura modified with the stacked oxide semiconductor layers of Jin discussed above)
Kimura and Jin both fail to explicitly disclose the device further comprising: a fourth conductive layer, wherein the fourth conductive layer comprises a region in contact with the top surface of the first conductive layer, and wherein a conductivity of the fourth conductive layer is higher than a conductivity of the first conductive layer.
However in the same field of endeavor, Yama2 discloses a device comprising: a fourth conductive layer (2143b Yama2 Fig 29B), wherein the fourth conductive layer comprises a region in contact with the top surface of the first conductive layer (first conductive layer 2143a Fig 29B), and wherein a conductivity of the fourth conductive layer is higher than a conductivity of the first conductive layer (“for the conductive layer 2143b, a conductive material having lower resistance than the conductive layer 2143a … is preferably used” [Yama2 0504]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device structure as disclosed in Kimura and modified by Jin to have an additional layer of conductive material stacked on top of the top surface of the first conductive layer, Kimura Fig 3A 111, around the region where the semiconductor layer 113 contacts the top surface of 111, so that the stacked conductive layers “can have extremely low resistance” [Yama2 0504].
Kimura modified by Jin as applied to claim 1 further modified by Yama2 thereby discloses the structure of the device in Kimura Fig 3A wherein the first insulating layer (Kimura Fig 3A 103) is in contact with the top surface of the first conductive layer (top surface of 111) and a top surface and a side surface of the fourth conductive layer (top surface and side surface of stacked conductive layer such as the one disclosed in Yama2 Fig 29B 2143b, having a higher conductivity than layer 111, thereby increasing conductivity and lowering resistance of the whole first conductive layer), wherein the fourth conductive layer (Yama2’s Fig 29B layer 2143b is overlapped in Kimura Fig 3A’s structure by the third conductor, gate electrode 115) and the third conductive layer (Kimura 115) overlap with each other with the first insulating layer (103), the first oxide semiconductor layer (first and second oxide semiconductor layer are in the location of Kimura’s semiconductor layer 113, but modified to have the stacked semiconductor oxide layers as disclosed in Jin), the second oxide semiconductor layer (as disclosed in Jin, in the location of Kimura’s Fig 3A layer 113), and the second insulating layer therebetween (Kimura Fig 3A insulating layer 105)(all four of those elements exist between the gate electrode Kimura Fig 3A 115 and the top surface of 111, where the additional conductive layer of Yama2 would be disposed in the modified structure).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki in view of Jin as applied to claim 1, further in view of Yamazaki et al. US 2022/0139917 A1 hereinafter “Yama2”.
Regarding claim 9, Sasaki in view of Jin discloses The semiconductor device according to claim 1, (Sasaki modified with the stacked oxide semiconductor layers of Jin discussed above)
Sasaki and Jin both fail to explicitly disclose the device further comprising: a fourth conductive layer, wherein the fourth conductive layer comprises a region in contact with the top surface of the first conductive layer, and wherein a conductivity of the fourth conductive layer is higher than a conductivity of the first conductive layer.
However in the same field of endeavor, Yama2 discloses a device comprising: a fourth conductive layer (2143b Yama2 Fig 29B), wherein the fourth conductive layer comprises a region in contact with the top surface of the first conductive layer (first conductive layer 2143a Fig 29B), and wherein a conductivity of the fourth conductive layer is higher than a conductivity of the first conductive layer (“for the conductive layer 2143b, a conductive material having lower resistance than the conductive layer 2143a … is preferably used” [Yama2 0504]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device structure as disclosed in Sasaki and modified by Jin to have an additional layer of conductive material stacked on top of the top surface of the first conductive layer, Sasaki Fig 129 120M, around the region where the semiconductor layer 160M contacts the top surface of 120M, so that the stacked conductive layers “can have extremely low resistance” [Yama2 0504].
Sasaki modified by Jin as applied to claim 1 further modified by Yama2 thereby discloses the structure of the device in Sasaki Fig 129 10M wherein the first insulating layer (Sasaki Fig 129 130M) is in contact with the top surface of the first conductive layer (top surface of 120M) and a top surface and a side surface of the fourth conductive layer (top surface and side surface of stacked conductive layer such as the one disclosed in Yama2 Fig 29B 2143b, having a higher conductivity than layer 120M, thereby increasing conductivity and lowering resistance of the whole first conductive layer), wherein the fourth conductive layer (Yama2’s Fig 29B layer 2143b is overlapped Sasaki Fig 129’s structure by the third conductor, gate electrode 180M) and the third conductive layer (Sasaki 180M) overlap with each other with the first insulating layer (130M), the first oxide semiconductor layer (first and second oxide semiconductor layer are in the location of Sasaki’s semiconductor layer 160M, but modified to have the stacked semiconductor oxide layers as disclosed in Jin), the second oxide semiconductor layer (as disclosed in Jin, in the location of Sasaki Fig 129 160M), and the second insulating layer therebetween (Sasaki Fig 129 second insulating layer 170M)(all four of those elements exist between the gate electrode Sasaki Fig 129 180M and the top surface of 120M, where the additional conductive layer of Yama2 would be disposed in the modified structure).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kimura in view of Yamazaki et al. US 2014/0070224 A1, hereinafter “Yamazaki”.
Regarding independent claim 10, Kimura discloses A semiconductor device comprising a transistor (Kimura Fig 3A, transistor 33, and Fig 3B shows two transistor structures 33a and 33b), the transistor comprising: a first conductive layer as one of a source electrode and a drain electrode of the transistor over a substrate (first conductive layer 111 in Fig 3A "functions as one of the source electrode of the drain electrode of the transistor 33a and one of the source electrode or the drain electrode of the transistor 33b" [Kimura 0108], over substrate 101;
a first insulating layer (Fig 3A layer 103) comprising a first opening (opening 121 in Figs 2-3) reaching the first conductive layer (Fig 3A);
a second conductive layer (112a and 112b Fig 3A) as the other of the source electrode and the drain electrode of the transistor ([0108]) over the first insulating layer and comprising a second opening (opening 123 in Fig 3A, overlapping opening 121) overlapping with the first opening;
a first oxide semiconductor layer (semiconductor layer 113) in contact with a top surface of the first conductive layer (contacts top surface of 111), a side surface of the first insulating layer (contacts sides of 103 in the opening), and a top surface and a side surface of the second conductive layer (contacts sides and tops of 112a and 112b);
However, Kimura does not disclose a second oxide semiconductor layer over the first oxide semiconductor layer; but in the same field of endeavor, Yamazaki discloses a similar device which utilizes a first oxide semiconductor layer (Yamazaki Fig 3A and 3B, multilayer film 111 containing oxide layer 111_1) and a second oxide semiconductor layer (Fig 3B 111_2) over the first oxide semiconductor layer (Yamazaki Fig 3B stacked films, first 111_1 and second 111_2); and wherein a crystallinity of the first oxide semiconductor (Fig 3B 111_1) layer is lower than a crystallinity of the second oxide semiconductor layer ("the first oxide layer 111_1 is preferably an oxide semiconductor having lower crystallinity than the second oxide layer 111_2" [Yamazaki 0104]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date to substitute the single oxide semiconductor layer 113 in Kimura Fig 3A with the two stacked oxide semiconductor layers as disclosed in Yamazaki to "to reduce variation in the electrical characteristics of the transistor, such as threshold voltage" [Yamazaki 0100].
Kimura modified by Yamazaki results in a second insulating layer over the second oxide semiconductor layer (insulating layer 105 Kimura Fig 3A); and a third conductive layer as a gate electrode of the transistor over the second insulating layer (conductive layer 115, the gate electrode stacked on top of the insulating layer 105), wherein each of the first oxide semiconductor layer, the second oxide semiconductor layer, the second insulating layer, and the third conductive layer comprises a region embedded in the first opening and the second opening (Kimura Fig 3A, elements 113, 105, and 115 are disposed in the opening 121, and Kimura modified to have the stacked layers of Yamazaki in place of element 113 would retain this structure).
Claim(s) 10 is further rejected under 35 U.S.C. 103 as being unpatentable over Sasaki in view of Yamazaki et al. US 2014/0070224 A1, hereinafter “Yamazaki”.
Regarding independent claim 10, Sasaki discloses A semiconductor device comprising a transistor (Sasaki Fig 129 transistor 10M), the transistor comprising: a first conductive layer as one of a source electrode and a drain electrode of the transistor over a substrate (lower electrode 120M which may serve as the source electrode [Sasaki 0040]);
a first insulating layer (Fig 129 130M) comprising a first opening (opening 139M) reaching the first conductive layer (Fig 129);
a second conductive layer (140M) as the other of the source electrode and the drain electrode of the transistor ([0040]) over the first insulating layer and comprising a second opening (opening 139M) overlapping with the first opening (overlap in Fig 129);
a first oxide semiconductor layer (160M) in contact with a top surface of the first conductive layer (contacts top surface of 120M), a side surface of the first insulating layer (contacts sides of 130M in the opening), and a top surface and a side surface of the second conductive layer (contacts sides and tops of 140M);
However, Sasaki does not disclose a second oxide semiconductor layer over the first oxide semiconductor layer; but in the same field of endeavor, Yamazaki discloses a similar device which utilizes a first oxide semiconductor layer (Yamazaki Fig 3A and 3B, multilayer film 111 containing oxide layer 111_1) and a second oxide semiconductor layer (Fig 3B 111_2) over the first oxide semiconductor layer (Yamazaki Fig 3B stacked films, first 111_1 and second 111_2); and wherein a crystallinity of the first oxide semiconductor (Fig 3B 111_1) layer is lower than a crystallinity of the second oxide semiconductor layer ("the first oxide layer 111_1 is preferably an oxide semiconductor having lower crystallinity than the second oxide layer 111_2" [Yamazaki 0104]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date to substitute the single oxide semiconductor layer 113 in Sasaki Fig 129 with the two stacked oxide semiconductor layers as disclosed in Yamazaki to "to reduce variation in the electrical characteristics of the transistor, such as threshold voltage" [Yamazaki 0100].
Sasaki modified by Yamazaki results in a second insulating layer over the second oxide semiconductor layer (insulating layer 170 M Sasaki Fig 129); and a third conductive layer as a gate electrode of the transistor over the second insulating layer (conductive layer 180M, the gate electrode stacked on top of the insulating layer 170M), wherein each of the first oxide semiconductor layer, the second oxide semiconductor layer, the second insulating layer, and the third conductive layer comprises a region embedded in the first opening and the second opening (Sasaki Fig 129, elements 160M, 170M, and 180M all comprise a region embedded in the opening 139M; therefore, Sasaki modified to have the stacked layers of Yamazaki in place of element 160M would retain this structure).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gwak et al. KR 10234767 B1 which discloses stacked semiconductor oxide layers over an electrode in Fig 4
Iida et al. WO 2019130161 A1 which discloses a device in Fig 1B with stacked oxide films over a first electrode, surrounded by second electrodes on the sides, and overlapped with the third electrode, with insulating layers therebetween
Sasaki et al. US 12302645 B2 which discloses in Fig 2B a lower electrode, semiconductor layer, insulating layer, and upper electrode with an opening in the upper electrode
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/TERESA N MICKEY/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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