Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
Applicants elect Group I (Claims 16-30) without traverse.
Claim Rejections – 35 U.S.C. 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cooper et al (2023/0084310).
Regarding Claim 16, Cooper et al (2023/0084310) discloses a filter module (filter circuitry, paragraph [0046]), comprising: a first ground layer (L3, GND, see upside down fig. 12); a second ground layer (L1, GND, fig. 12) disposed so as to be spaced apart from the first ground layer; a first conductive pattern layer (L2, SIG, fig. 12) disposed between the first ground layer (L3, GND) and the second ground layer (L1, GND); a second conductive pattern layer (L4, SIG) disposed on one side of the first ground layer (L3) or the second ground layer; and a via interconnecting (see the dotted line goes through all layers) at least two of the first ground layer (L3), the second ground layer (L1), the first conductive pattern layer (L2), and the second conductive pattern layer (L4).
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Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17-19, 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cooper et al (2023/0084310).
Regarding Claim 17, Cooper does not explicitly disclose the filter module according to claim 16, wherein the first conductive pattern layer includes a capacitance pattern formed to have a capacitance while facing at least one of the first ground layer or the second ground layer.
However, Cooper discloses the filter circuitry comprising capacitors and inductors and resistors (paragraph [0051], L2 (as first conductive pattern layer) and L4 (as second conductive pattern layer) are signal layers (paragraph [0125]).
It would have been obvious to one of ordinary skill in the art to have composed or printed the filter circuitry on L2 in order to filter the signal that is received at the signal layer.
Regarding Claim 18, Cooper discloses the filter module according to claim 17, wherein the first conductive pattern layer includes a first inductance pattern formed to have an inductance (paragraph [0051]).
Regarding Claim 19, Cooper does not explicitly disclose the filter module according to claim 17, wherein the second conductive pattern layer includes a second inductance pattern formed to have an inductance.
However, Cooper discloses the filter circuitry comprising capacitors and inductors and resistors (paragraph [0051], L2 (as first conductive pattern layer) and L4 (as second conductive pattern layer) are signal layers (paragraph [0125]).
It would have been obvious to one of ordinary skill in the art to have composed or printed the filter circuitry on L2 in order to filter the signal that is received at the signal layer.
Regarding Claim 30, Cooper discloses a filter module (filter circuitry, paragraph [0046]), comprising: a second ground layer (L1, GND, fig. 12); a first conductive pattern layer (L2, SIG) stacked on the second ground layer (L1, GND), the first conductive pattern layer (L2, SIG); a first ground layer (L3) stacked on the first conductive pattern layer (L2); a second conductive pattern layer (L4) stacked on the first ground layer (L3), the second conductive pattern layer (L4) including a transmission line (L1-L3 may form the RF transmission line paths, paragraph [0126]) the first conductive pattern layer (L2) and the second conductive pattern layer (L4) in a vertical direction.
Cooper does not explicitly disclose the pattern layers implementing an inductor and a capacitor.
However, Cooper discloses the filter circuitry comprising capacitors and inductors and resistors (paragraph [0051], L2 (as first conductive pattern layer) and L4 (as second conductive pattern layer) are signal layers (paragraph [0125]).
It would have been obvious to one of ordinary skill in the art to have composed or printed the filter circuitry on L2 in order to filter the signal that is received at the signal layer.
Allowable subject matter
Claims 20-29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner Wilson Lee whose telephone number is (571) 272-1824. Proposed amendment and interview agenda can be submitted to Examiner’s direct fax at (571) 273-1824.
If attempts to reach the examiner by telephone are unsuccessful, examiner’s supervisor, Alexander Taningco can be reached at (571) 272-8048. Papers related to the application may be submitted by facsimile transmission. Any transmission not to be considered an official response must be clearly marked "DRAFT". The official fax number is (571) 273-8300.
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/WILSON LEE/Primary Examiner, Art Unit 2845
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