CTNF 18/865,781 CTNF 100160 DETAILED ACTION This action is responsive to the following communications: the Application filed on November 14, 2024, the PCT/JP2023/012469 filed on March 28, 2023, the Foreign Priority papers retrieved on May 23, 2022 and the Information Disclosure Statement filed on November 14, 2024. Claims 1-14 are pending. Claim 1 is independent. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority 02-26 AIA Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on November 14, 2024. This IDS has been considered. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-2 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Maruyama et al. (US 20030156478) . Regarding independent claim 1, Maruyama et al. disclose a non-volatile storage device [see Fig. 3] comprising: memory cells that are arranged in a matrix in a row direction [see Fig. 3, TWL0 to TWL3 are word lines that are connected to the control gates of the memory cells (Ma0, Mb0) to (Ma3, Mb3), respectively, which are arranged in a line in the row direction between the memory cell blocks 10a and 10b, para. 51] and a column direction [see Fig. 3, the memory cell unit UNIT-A has four memory cell blocks 10a to 10d arranged in an array, and each memory cell block 10a to 10d respectively has four memory cells Ma0 to Ma3, Mb0 to Mb3, Mc0 to Mc3, and Md0 to Md3, which are nonvolatile semiconductor memory elements arranged in the column direction, para. 47] and store data [para. 48] used to generate a data potential [sense amplifier circuit SAMP to compare the potentials of the main bit line MBL0 and anti-main bit line MBL1, amplify this difference, and perform data readout, para. 64] transmitted in the column direction [sub-bit lines SBL0-SBL3 of the memory cell blocks arranged in a line in the column direction are connected to main bit line MBL0 or anti-main bit lines MBL1, para. 50]; and reference memory cells that are dispersedly arranged in the column direction [see Fig. 3, each memory cell block 10a to 10d respectively has four memory cells Ma0 to Ma3, Mb0 to Mb3, Mc0 to Mc3, and Md0 to Md3, which are nonvolatile semiconductor memory elements arranged in the column direction, and one reference cell RCa0, RCb0, RCc0, and RCd0, respectively, para. 47. Sub-bit line SBL1 to SBL3 respectively arranged in the blocks is connected to the drain sides of the respective memory cells and reference cell within the blocks, para. 49] and store reference data used to generate a standard potential at a time of detection of the data stored in the memory cells [when the data readout operation is performed while an equal amount of current is supplied to the main bit line MBL0 and the anti-main bit line MBL1 from the bit line current supply circuit BLCASS, the potential Reference of the anti-main bit line MBL1, to which the reference cell RCd0 is connected, is maintained substantially at the precharge voltage, para. 63. Sense amplifier circuit SAMP to compare the potentials of the main bit line MBL0 and anti-main bit line MBL1, amplify this difference, and perform data readout, para. 64]. Regarding claim 2, Maruyama et al. disclose wherein a plurality of the memory cells is continuously arranged between the reference memory cells along the column direction [see Fig. 3, the memory cell unit UNIT-A has four memory cell blocks 10a to 10d arranged in an array, and each memory cell block 10a to 10d respectively has four memory cells Ma0 to Ma3, Mb0 to Mb3, Mc0 to Mc3, and Md0 to Md3, which are nonvolatile semiconductor memory elements arranged in the column direction, and one reference cell RCa0, RCb0, RCc0, and RCd0, respectively, para. 47. In the memory cell block 10a, a single sub-bit line SBL0 is connected to the drain sides of the memory cells Ma0 to Ma3 and the reference cell RCa0, para. 49. Sub-bit lines SBL0-SBL3 of the memory cell blocks arranged in a line in the column direction are connected to main bit line MBL0 or anti-main bit lines MBL1, para. 50] . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 3-8 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Maruyama et al. (US 20030156478) as applied to claim 1 above, in view of Guo (US 20220343960) . Regarding claim 3, Maruyama et al. teach the limitations with respect to claim 1. Furthermore, Maruyama et al. disclose some decoder circuits for selecting word lines, reference word lines, columns gates and source lines [see Fig. 3, para. 56]. However, Maruyama et al. are silent with respect to further comprising a selection control circuit that controls a selection position of the reference memory cells on a basis of a selection position of the memory cells from which the data is read. Guo teaches a non-volatile storage device [Fig. 2B: 201] further comprising a selection control circuit [Fig. 2B: 211] that controls a selection position of the reference memory cells on a basis of a selection position of the memory cells from which the data is read [when a data column is selected for a read/write operation, the column MUX 211 can select the closest reference columns to the data column being read to generate the reference signal. This ensures that the overall RC pathway experienced by the logic 0/1 reference signals experience the same resistance and capacitance loads as the read data, para. 40. Each data column may be assigned to a specific reference column that is in the same sector of the memory array, para. 60]. It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Guo to the teaching of Maruyama et al. such that modifying the non-volatile storage device of Maruyama et al. with a selection control circuit that selects position of the reference memory cells based on the selected memory cell position from which the data is read as taught by Guo to improve read margin and sensing accuracy. Regarding claim 4, Maruyama et al. teach the limitations with respect to claim 1. Furthermore, Maruyama et al. disclose further comprising: a word line that selects the memory cells in the row direction [see Fig. 3, WL is the word line connected to the control gates of the memory cells 1 lined up in the row direction, para. 41]; a reference word line that selects the reference memory cells in the row direction [see Fig. 3, RWL is a reference word line connected to the gates of the reference cells 2 arranged in a line in the row direction, para. 41]; a standard potential generation circuit that generates the standard potential on a basis of a reference potential transmitted in the column direction [Maruyama et al. disclose a reference potential generated by a reference cell RDd0 and transmitted on the anti-main bit line MBL1, then used for comparison by the sense amplifier circuit SAMP, para. 63-64]; a sense amplifier that detects the data read from the memory cells on a basis of the data potential and the standard potential [see Fig. 3, the sense amplifier circuit SAMP is controlled by two control signals SAE and SAEN, and determines and amplifies the potential difference between the main bit line MBL0 and the anti-main bit line MBL1 when the control signal SAE is H-level and the control signal SAEN is L-level, para. 52 and 64]; and a reference word line driver that drives the reference word line selected [see Fig. 3, the numeral 7 denotes a pre-decoder and 8 denotes a row decoder for selecting the word lines TWL0 to BWL3 and the reference word lines TRWL0 and BRWL0, para. 56]. However, Maruyama et al. are silent with respect to comprising a reference word line driver that drives the reference word line selected on a basis of a selection position of the word line connected to the memory cells from which the data is read. Guo teaches selecting reference structures based on the selected data position so the reference and data signals share similar resistance and capacitance (RC) pathway [para. 31 and 38-41]. It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Guo to the teaching of Maruyama et al. such that modifying the non-volatile storage device of Maruyama et al. with a reference word line driver that drives the reference word line selected based on the selection position of the word line connected to the memory cells from which the data is read as taught by Guo to improve read margin and sensing accuracy through predictable path matching results. Regarding claim 5, Maruyama et al. in combination with Guo teach the limitations with respect to claim 4. Furthermore, Maruyama et al. disclose further comprising a bit line commonly used for transmission of the data potential in the column direction and transmission of the reference potential in the column direction [in the memory cell block 10a, a single sub-bit line SBL0 is connected to the drain sides of the memory cells Ma0 to Ma3 and the reference cell RCa0 and similarly for other blocks, para. 49. Those sub-bit lines SBL0-SBL3 of the memory cell blocks arranged in a line in the column direction are connected to main bit line MBL0 or anti-main bit lines MBL1, para. 50], wherein the sense amplifier includes a data terminal connected to a bit line used for transmission of the data potential [the main bit line MBL0 and the anti-main bit line MBL1 are connected to the differential sense amplifier circuit SAMP via column gates Y0 and Y1, para. 52. The sense amplifier circuit SAMP to compare the potentials of the main bit line MBL0 and anti-main bit line MBL1, amplify this difference, and perform data readout, para. 64], and a reference terminal connected to a bit line used for transmission of the reference potential [the anti-main bit line MBL1 connected to reference cell RCd0 and having the reference potential, para. 63]. Regarding claim 6, Maruyama et al. in combination with Guo teach the limitations with respect to claim 4. Furthermore, Guo discloses the standard potential generation circuit generates the standard potential on a basis of averaging of a plurality of the reference potentials transmitted through bit lines different from each other [Guo discloses averaging or combining output currents from a plurality of reference columns to generate the final reference signal, para. 61]. Regarding claim 7, Maruyama et al. in combination with Guo teach the limitations with respect to claim 4. Furthermore, Maruyama et al. disclose the reference word line driver drives only one reference word line connected to the reference memory cells from which the reference data is read when the standard potential is generated [RWL is a reference word line connected to the gates of the reference cells 2 arranged in a line in the row direction, para. 41. The selected word line TWL0 is set to H-level to select the memory cell Ma0 for data readout. At the same time, the selected word line BRWL0 is set to H-level to select the reference cell RCd0, para. 63]. Regarding claim 8, Maruyama et al. in combination with Guo teach the limitations with respect to claim 7. Furthermore, Guo discloses the reference word line driver drives the reference word line closest to the word line connected to the memory cells from which the data is read with respect to a distance in the column direction to the sense amplifier [The column multiplexer 210 can select a reference current from one of the reference columns 208 that is physically closest to the data column 206 that is being read, para. 31. When a data column is selected for a read/write operation, the column MUX 211 can select the closest reference columns to the data column being read. This ensures that the overall RC pathway experienced by the logic 0/1 reference signals experience the same resistance and capacitance loads as the read data, para. 40]. Regarding claim 10, Maruyama et al. in combination with Guo teach the limitations with respect to claim 4. Furthermore, Guo discloses each of the memory cells and the reference memory cells include magnetoresistive memories [see Fig. 1A, MRAM cell 170], and resistance values of the magnetoresistive memories are combined [Guo discloses combining the reference columns by summing or aggregating voltage or current outputs and scaling them to generate an average reference signal between logic 0 and logic 1, para. 37] and stored in a plurality of the reference memory cells connected to the reference word line [as part of each read/write operation, the reference cells 250-257 in the reference columns can store or refresh along with the data in the data cell 258, para. 46]. Regarding claim 11, Maruyama et al. in combination with Guo teach the limitations with respect to claim 4. Furthermore, Maruyama et al. disclose the reference word line driver drives a plurality of the reference word lines connected to the reference memory cells from which the reference data is read when the standard potential is generated [TRWL0 and BRWL0 are reference word lines connected to the gates of the reference cells RCa0, RCb0, RCc0, and RCd0, para. 51. The numeral 7 denotes a pre-decoder and 8 denotes a row decoder for selecting the word lines TWL0 to BWL3 and the reference word lines TRWL0 and BRWL0, para. 56. With the word lines TWL0 to TWL3 and BWL0 to BWL3, the reference word lines TRWL0 and BRWL0, and the selection signal lines TSG0, TSG1, BSG0, and BSG1 at the L-level, the control signals PCN0 and PCN1 are set to the L-level to activate the precharge circuits PreCHG0 and PreCHG1 and precharge the main bit line MBL0 and the anti-main bit line MBL1 to a predetermined voltage, para. 60] . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 9 and 12-14 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: With respect to claim 9, there is no teaching or suggestion in the prior art of record to provide the recited the reference word line driver drives the reference word line on a basis of high-order bits of an address for selecting the memory cells. With respect to claim 12, there is no teaching or suggestion in the prior art of record to provide the recited the reference word line driver drives the reference word lines on a basis of at least one of high-order bits of an address for selecting the memory cells or a combination signal for designating a combination of the plurality of reference word lines . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached at (571)272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DUY H LUONG/Examiner, Art Unit 2825 /ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825 Application/Control Number: 18/865,781 Page 2 Art Unit: 2825 Application/Control Number: 18/865,781 Page 3 Art Unit: 2825
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