DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed July 8, 2026 have been fully considered but they are not persuasive. Applicant argues that the claimed invention comprises a dual path PLL that comprises a first digital component called the “integral path” and a second analog component called the “proportional path” that operate in parallel to produce two distinct frequency control signals which are both input to the oscillator, features which applicant states are not taught by the prior art of record.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., two distinct components creating two distinct oscillator inputs) are not recited in the rejected claims. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). In this application, what is claimed are “paths” through circuitry that perform the functions of comparing a reference signal and a non-delayed feedback signal and comparing the reference signal to a delayed feedback signal for the purpose of generating oscillator control signals that lock the phase of the output signal to the phase of the reference signal. Applicant’s analysis of the prior art in comparison to the claimed invention operates off the assumption that the claimed paths are separate and distinct circuits operating in parallel and producing two independent outputs. The scope of the claimed invention, however, only recites circuitry comprising paths that perform a first function of comparing the reference signal to a non-delayed feedback signal and a second function of comparing the reference signal to a delayed feedback signal. This scope includes embodiments where said paths are in series rather than parallel, said paths can further include the claimed delay circuit, and the delayed feedback signal could itself be the first frequency control signal. The prior art cited performs the claimed functions of first comparing the reference signal to a non-delayed feedback signal (Cherniak, inputs to DTC, fig. 3A) along a circuit path and further performs the function of comparing the reference signal to a delayed feedback signal (Cherniak, inputs to TDC, where FDIV is shown to be delayed by a delay circuit in fig. 3B). Applicant is advised to simply amend the claimed invention to reflect what is described in the specification and argued by applicant in the outstanding response. Said amendments comprise specifying the delay circuit, “integral path”, and “proportional path” are separate and distinct elements operating in parallel producing two separate oscillator control outputs as clearly shown in fig. 5 of the originally filed specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 24-38 and 40-46 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cherniak et al. (11,418,199, of record) [Cherniak].
Regarding claims 24, 41, 42, 45, and 46, Cherniak discloses a dual path Phase Locked Loop (PLL) circuit configured to minimize phase error between a periodic output signal and a reference signal (fig. 3A), comprising:
a controlled oscillator circuit configured to generate the periodic output signal in response to frequency control inputs (fig. 3A DCO 310);
a frequency divider circuit configured to divide the periodic output signal by a divisor to generate a non-delayed feedback signal (fig. 3A quantizer 316, summer 318, and MMD 314, col. 5 lines 45-48, are the digital equivalents of divider 108 shown in fig. 1A);
a delay circuit configured to delay the non-delayed feedback signal and generate a delayed feedback signal (fig. 3A TDC 304, shown in more detail in fig. 3B with delay circuits 332- 336, col. 6 lines 16-42);
an integral path of circuitry configured to receive the periodic reference signal and the non-delayed feedback signal, and to generate a first frequency control signal for the controlled oscillator based on a phase difference between the periodic reference signal and the non- delayed feedback signal, so as to lock the phase of the periodic output signal to the phase of the reference signal (fig. 3A DTC 302, col. 6 lines 28-53); and
a proportional path of circuitry configured to receive the periodic reference signal and the delayed feedback signal, and to generate a second frequency control signal for the controlled oscillator based on a phase difference between the periodic reference signal and the delayed feedback signal (fig. 3B, col. 6 line 53 - col. 7 line 23).
Regarding claim 25, Cherniak discloses the PLL circuit of claim 24 wherein the divisor of the frequency divider circuit is an integer (col. 5 line 61 - col. 6 line 15).
Regarding claim 26, Cherniak discloses the PLL circuit of claim 24, wherein the divisor of the frequency divider circuit includes a fractional component (col. 5 line 61 - col. 6 line 15).
Regarding claim 27, Cherniak discloses the PLL circuit of claim 24, wherein the integral path of circuitry includes a binary phase detector configured to output an indication of a difference in phase between the reference signal and the non-delayed feedback signal (col. 6 lines 28-53).
Regarding claim 28, Cherniak discloses the PLL circuit of claim 27, wherein the integral path of circuitry comprises digital circuitry (circuitry is all digital, col. 5 lines 33-35).
Regarding claim 29, Cherniak discloses the PLL circuit of claim 24, wherein the proportional path of circuitry comprises a first edge triggered phase detector configured to receive the reference signal and the delayed feedback signal, and to output a plurality of phase error pulses, a width of each phase error pulse indicating at least a difference in phase between the reference signal and the delayed feedback signal (fig. 3B, outputs of delay circuits 332-336).
Regarding claim 30, Cherniak discloses the PLL circuit of claim 29, wherein the proportional path of circuitry comprises analog circuitry (fig. 1A is an analog equivalent to the digital implementation of fig. 3A).
Regarding claim 31, Cherniak discloses the PLL circuit of claim 29, wherein the proportional path of circuitry further comprises: a charge pump connected to the output of the first phase detector; and a filter connected to the output of the charge pump and configured to output a proportional frequency correction signal to the controlled oscillator; wherein the phase error pulses cause the charge pump to output one of positive and negative current, but not both, to the filter (tuning voltage produced by analog implementation, fig. 2A col. 5 lines 16-32).
Regarding claim 32, Cherniak discloses the PLL circuit of claim 29 wherein a phase error to proportional frequency correction transfer function exhibits greater linearity than a corresponding transfer function in a PLL circuit without the delay of the feedback signal (col. 6 line 53 - col. 7 line 23).
Regarding claim 33, Cherniak discloses the PLL circuit of claim 31, wherein the proportional path of circuitry is further configured to receive the non-delayed feedback signal (fig. 3B, FREF received from DTC 302), and wherein the proportional path of circuitry further comprises: a second edge triggered phase detector configured to receive the non-delayed feedback signal and the delayed feedback signal, and to output a plurality of phase error pulses, a width of each phase error pulse indicating a difference in phase between the non-delayed feedback signal and the delayed feedback signal (any number of delay circuits may be used, col. 7 lines 13-16).
Regarding claims 34 and 43, Cherniak discloses the PLL circuit and method of claims 33 and 42, further comprising an adder configured to combine phase error pulses output by the first and second phase detectors, and wherein the width of phase error pulses output by the first phase detector is effectively reduced by the width of phase error pulses output by the second phase detector (fig. 3A, adder 306).
Regarding claim 35, Cherniak discloses the PLL circuit of claim 33, wherein the second phase detector outputs only phase error pulses indicating that the non-delayed feedback signal leads the delayed feedback signal in phase (pulses only indicate a lead, as a lag has an output of zero, col. 6 line 66 - col. 7 line 11).
Regarding claim 36, Cherniak discloses the PLL circuit of claim 33, wherein one of the first and second phase detectors includes an added propagation delay configured to equalize the frequency correction signals output by the integral and proportional paths of circuitry (col. 6 line 53 - col. 7 line 23).
Regarding claims 37, 40, and 44, Cherniak discloses the PLL circuit and method of claims 33 and 43, further comprising a timing skew feedback loop in the proportional path of circuitry, comprising: a low pass filter connected across a terminal resistor of the filter; a comparator connected to the low pass filter and configured to output a binary indication of a polarity of a low-pass filtered voltage across the terminal resistor of the filter; and a control circuit configured to generate a timing skew control signal in response to the binary indication of polarity; wherein the control circuit is configured to strive for zero voltage across the terminal resistor of the filter and the timing skew control signal is added to the output of the binary phase detector in the integral path of circuitry (fig. 3A, conventional digital loop filter 308, col. 5 lines 49-60).
Regarding claim 38, Cherniak discloses the PLL circuit of claim 37, wherein the control circuit implements a binary search algorithm (digital filter, rather than analog, col. 5 lines 49-60).
Allowable Subject Matter
Claim 39 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Said claim introduces a third delay via the use of a timing skew circuit that is applied to an already delayed feedback signal. This does not appear to be taught or reasonably suggested in the prior art at the time of effective filing. Said prior art teaches that such a timing skew circuit is a part of the process for providing the delayed feedback signal itself via the use of conventional output filtering (see rejection of claim 37).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOMINIC D SALTARELLI whose telephone number is (571)272-7302. The examiner can normally be reached 9:00 am - 5:00 pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nathan Flynn can be reached at (571) 272-1915. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DOMINIC D SALTARELLI/Primary Examiner, Art Unit 2421
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