DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Yan et al. (US 20150009379 A1; hereinafter CHO) in view of Azami (US 20100091167 A1).
As of Claim 1: Yan teaches in FIGS. 1, 3, 8 a solid-state imaging device (¶0026, CMOS imager ) comprising: a photoelectric conversion element (¶0028 and a photodiode D1);
a charge-voltage conversion unit that converts charge photoelectrically converted by the photoelectric conversion element into a voltage (¶0028 and floating diffusion region FD);
a capacitor that is connected to the charge-voltage conversion unit and adjusts a voltage level of the charge- voltage conversion unit (¶0028 and C1 coupled between floating diffusion region C1 and ground. Capacitor C1 may be a discrete capacitor component or may be formed from parasitic capacitances such as associated with the gate of transistor M3. Pixel 120 may include a capacitor C6 through which a ramp signal is applied to floating diffusion region FD.);
a first semiconductor layer in which at least one of the photoelectric conversion element or the capacitor is arranged (¶0031 and circuitry 107A to perform sample and hold operations. Sample and hold circuitry 107B may receive ramp signal VR from ramp circuitry 136 via path 134 in performing sample and hold operations. Ramp circuitry 136 may be formed as part of pixel array 101 or may be included in row driver circuitry such as row driver circuitry 102 of FIG. 2. Ramp signal path 134 may extend across the row of pixel 120 (e.g., signal path 134 may be coupled to and provide ramp signal VR to each pixel of the row);
Azami is a similar or analogous system to the claimed invention as evidenced Azami teaches a plurality of counters that count the comparing time of a corresponding comparator. Each comparator includes: a first amp containing a differential amplifier that receives the reference voltage at the gate of a transistor, receives the readout signal at the gate of another transistor, and compares the reference voltage to the readout signal potential that would have prompted a predictable variation of Yan by applying Azami’s known principal of a signal line that transmits a pixel signal according to the voltage level of the charge-voltage conversion unit (¶¶0053,0064); and
a comparator that is arranged on the signal line and compares the pixel signal with a predetermined reference signal (¶¶0062,0065,0068,0073 and note that The comparator 200A shown in FIG. 14 is configured such that the polarity of the transistors is the reverse of that of the comparator 200 shown in FIG. 4. For this reason, the connected power supply potential and ground potential are also reversed in the circuit. For the sake of simplicity, the reference numbers for the nodes and capacitors).
In view of the motivations such as reducing noise while keeping the inversion time of the comparator short thereby further a camera system wherein frame rate can be improved without increasing circuit area, and able to reduce AD converter noise and one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Yan.
Therefore, the claimed invention would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention
As of Claim 2: Yan in view of Azami further teaches a reference signal generation unit that generates a reference signal whose voltage level is changeable with time, wherein the capacitor adjusts the voltage level of the charge- voltage conversion unit on a basis of the reference signal (Azami ¶¶0053,0062,0065 and note that comparator 151, which compares a reference voltage Vslop to an analog signal (i.e., a potential VSL). The reference voltage Vslop has a ramp waveform obtained by stepwise variation of a reference voltage generated by the DAC 161. ).
As of Claim 3: Yan in view of Azami further teaches a switching element that is connected to the capacitor and increases or decreases a voltage level of the capacitor while the switching element continues to be turned on or off (Azami ¶¶0019,0020 and note that Each comparator includes: a first amp containing a differential amplifier configured to receive the reference voltage at the gate of a transistor, receive the readout signal at the gate of another transistor, and compare the reference voltage to the readout signal potential; a second amp containing an amplifier configured to increase the gain of the output of the first amp, and output the result; and a capacitor connected between the input and the output of the amplifier in the second amp in order to exhibit the Miller effect).
Claims 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yan et al. (US 20150009379 A1; hereinafter CHO) in view of Azami (US 20100091167 A1), and further in view of HOSOGAI et al. (US 20220028782 A1; hereafter HOSOGAI).
As of Claim 7:HOSOGAI is a similar or analogous system to the claimed invention as evidenced Azami teaches a plurality of counters that count the comparing time of a corresponding comparator. Each comparator includes: a first amp containing a differential amplifier that receives the reference voltage at the gate of a transistor, receives the readout signal at the gate of another transistor, and compares the reference voltage to the readout signal potential that would have prompted a predictable variation of Yan by applying HOSOGAI’s known principal of a first wiring layer and a second wiring layer stacked on the first semiconductor layer; and an insulator layer arranged between the first wiring layer and the second wiring layer, wherein the capacitor includes the first wiring layer, the second wiring layer, and the insulator layer (¶0030 and note that FIG. 1, the first wiring layer 4 is formed on the first surface 2a of the semiconductor substrate 2. The first wiring layer 4 covers the trench capacitor 3. The second wiring layer 5 is formed on the second surface 2b of the semiconductor substrate 2. The first wiring layer 4 includes an insulator layer in which a plurality of wirings such as wirings 4a and 4b are embedded. The second wiring layer 5 includes an insulator layer in which a plurality of wirings such as wirings 5a and 5b are embedded).
In view of the motivations such as stacking capacitors reducing noise while keeping the inversion time of the comparator short thereby stabilizing voltage supplied to an image unit and achieving a stable image signal and one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Yan.
As of Claim 8: Yan in view of Azami in view of HOSOGAI further teaches pixels including the photoelectric conversion element, the capacitor, and a pixel circuit are arranged in the first semiconductor layer (HOSOGAI ¶¶0024,0028,0030,0035 and note that the first and second connecting terminals 21 and 22 may be arranged on the front surface of the semiconductor substrate 2. Also, plurality of trench capacitors 3 may be divided into a plurality of groups of trench capacitors 3 when arranging these trench capacitors 3. For example, each group of trench capacitors 3 may include at least three (3) to ten (10) trench capacitors 3. FIG. 1 shows a first group of trench capacitors 3 (only three trench capacitors 3 are shown at the left side in a cross-sectional view). The first group of trench capacitors 3 may share one second electrode 3c.)
As of Claim 9: Yan in view of Azami in view of HOSOGAI further teaches the capacitor and the charge-voltage conversion unit are provided for each of the pixels (Yan¶¶0027,0028).
As of Claim 10: Yan in view of Azami in view of HOSOGAI further teaches the capacitor and the charge-voltage conversion unit are shared by a plurality of the pixels (Yan¶¶0030, 0032).
Allowable Subject Matter
Claims 4-6,11-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record fails to teach or fairly suggest all limitations of each of claims 11-18 in combination with their corresponding independent claim 1 as recited in the claims. Claims 4-6 depend from claim 2. Claims 13&14 depend from claim 12. Claims 9&10 depend from claim 8.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MEKONNEN D DAGNEW whose telephone number is (571)270-5092. The examiner can normally be reached on 8:00AM-5:00PM M-Th.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lin Ye can be reached on 571-272-7372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MEKONNEN D DAGNEW/Primary Examiner, Art Unit 2638
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