CTNF 18/869,694 CTNF 83209 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claim 46 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. a) regarding claim 46: Claim 46 depends on canceled claim 3 and is therefore indefinite. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 30-32, 43, 45 and 47-49 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Lye et al. (US Patent No. 9,225,507) . a) regarding claims 30 and 47-49: Lye et al. discloses User Equipment (UE) or a base station, operative in a wireless communication network (column 1, lines 6-27), the UE or base station including one or more transceiver circuits (Figure 3) including a pairwise phase difference regulation system (Figure 8) and method comprising: first and second Phase Locked Loops (PLL) (851 and 852) each comprising a controlled oscillator (403) configured to generate an output periodic signal that is phase-locked to a reference periodic signal (301), in response to a reference tracking feedback loop (313); a first phase difference detector (803) configured to receive a first periodic signal from the first PLL (851) and a second periodic signal from the second PLL (852), and output one or more error signals (804) representing a deviation from a targeted phase difference between the first and second periodic signals, and identifying which of the first and second periodic signals leads in phase (column 10, lines 53-57); wherein each of the first and second PLLs (851 and 852) is configured to control its oscillator (403) in response to both the one or more error signals representing a phase difference between the first and second periodic signals and its reference tracking feedback loop (column 10, lines 58-column 11, line 2); whereby the first phase difference detector (803) and first and second PLLs (851 and 852) form a pairwise phase difference feedback loop operative to minimize a deviation from a targeted phase difference between the output periodic signals of the first and second PLLs (column 10, lines 47-57 and 62-65). b) regarding claim 31: Lye et al. discloses the pairwise phase difference regulation system of claim 30, wherein the first and second periodic signals are the output periodic signals of the first and second PLLs (851 and 852). c) regarding claim 32: Lye et al. discloses the pairwise phase difference regulation system of claim 30, wherein the first and second periodic signals are divided (via 711) output periodic signals of the first and second PLLs. d) regarding claim 43: Lye et al. discloses the pairwise phase difference regulation system of claim 30, wherein the targeted phase error between the output periodic signals of two PLLs in a pairwise difference feedback loop is zero (column 10, lines 53-57). e) regarding claim 45: Lye et al. discloses the pairwise phase difference regulation system of claim 32, wherein each PLL includes a fractional-N frequency divider (604) in its reference tracking feedback loop (313), and an integer frequency divider (711) to generate the periodic signal in the pairwise phase difference feedback loop . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 33-42 and 44 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to disclose or make obvious a pairwise phase difference regulation system, wherein the first and second periodic signals are obtained by dividing the output periodic signal of the respective PLL by different numbers, the numbers having an integer ratio no larger than 10, or a rational ratio with the numerator and denominator being integers no larger than 10, along with all the other limitations as required by claim 33. The prior art of record fails to disclose or make obvious a pairwise phase difference regulation system wherein, for each of the first and second PLLs, the pairwise difference feedback loop has a higher bandwidth than the reference tracking feedback loop, along with all the other limitations as required by claim 34. The prior art of record fails to disclose or make obvious a pairwise phase difference regulation system, further characterized by a gain circuit interposed in a path of the one or more error signals output by the first phase difference detector, along with all the other limitations as required by claim 36. The prior art of record fails to disclose or make obvious a pairwise phase difference regulation system, wherein the one or more error signals comprise one error signal, wherein a magnitude of the error signal indicates the phase difference of the first and second periodic signals, and a polarity of the error signal indicates which of the first and second periodic signals leads in phase, along with all the other limitations as required by claim 37. The prior art of record fails to disclose or make obvious a pairwise phase difference regulation system, wherein the one or more error signals comprise first and second error signals, each having the same magnitude indicative of the detected deviation but different polarities, and each routed to a different one of the first and second PLLs; and the error signal polarity indicates whether the respective first or second periodic signal leads in phase, along with all the other limitations as required by claim 40. The prior art of record fails to disclose or make obvious a pairwise phase difference regulation system, further comprising: a third PLL comprising a controlled oscillator configured to generate an output periodic signal that is phase-locked to the reference periodic signal, in response to a reference tracking feedback loop; a second phase difference detector configured to receive the second periodic signal and a third periodic signal from the third PLL, and output one or more error signals representing a deviation from a targeted phase difference between the second and third periodic signals, and identifying which of the second and third periodic signals leads in phase; wherein the second PLL is further configured to control its oscillator also in response to the one or more error signals representing a phase difference between the second and third periodic signals; and wherein the third PLL is configured to control its oscillator in response to both the one or more error signals representing a phase difference between the second and third periodic signals and its reference tracking feedback loop; whereby the second phase difference detector and second and third PLLs form a pairwise difference feedback loop operative to minimize a deviation from a targeted phase error between the output periodic signals of the second and third PLLs, along with all the other limitations as required by claim 42. The prior art of record fails to disclose or make obvious a pairwise phase difference regulation system, wherein weights are applied to the phase difference error signals in response to the number of pairwise difference feedback loops in which a PLL participates, along with all the other limitations as required by claim 44 . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Patrick O'Neill whose telephone number is (571)270-1677. The examiner can normally be reached Monday- Friday 9AM-5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached at (571)270-7166. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICK O NEILL/Primary Examiner, Art Unit 2836 Application/Control Number: 18/869,694 Page 2 Art Unit: 2836 Application/Control Number: 18/869,694 Page 3 Art Unit: 2836 Application/Control Number: 18/869,694 Page 4 Art Unit: 2836 Application/Control Number: 18/869,694 Page 5 Art Unit: 2836 Application/Control Number: 18/869,694 Page 6 Art Unit: 2836 Application/Control Number: 18/869,694 Page 7 Art Unit: 2836
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