DETAILED ACTION
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Election/Restrictions
Applicant’s election without traverse of claims 1-5 and 8-13 in the reply filed on 08/31/2026 is acknowledged.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: --SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS COMPRISING A PLURALITY OF FUSES WITH A COMMON SWITCHING ELEMENT--
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 10 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim(s) 10 recite(s) the language (emphasis added) “in which electromigration is caused by application of a voltage”, where “a voltage” has already been recited in claim 9 and it is unclear if the voltages are different.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 and 9-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ashizawa, US 20070230079 A1.
As to claim 1, Ashizawa discloses a semiconductor device (see Ashizawa Para [0029]) comprising:
a plurality of fuse elements (see Ashizawa Fig 6 Refs FA0 and FB0); and a selection element (see Ashizawa Fig 6 Ref T1-0) that is provided in common (see Ashizawa Fig 6 the node left for Ref INV0) to the plurality of fuse elements and switches the plurality of fuse elements between a conduction target and a non-conduction target (see Ashizawa Paras [0040] and [0041]).
As to claim 2, Ashizawa discloses the semiconductor device according to claim 1, wherein
the plurality of fuse elements each include a filament (see Ashizawa Paras [0040] and [0041]; The blown out portion of the fuse is the filament.), an anode, and a cathode, and the plurality of fuse elements share the anode or the cathode (see annotated image of Ashizawa Fig 6 below).
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As to claim 3, Ashizawa discloses the semiconductor device according to claim 2, wherein
the selection element is a selection transistor having a drain and a source (see Ashizawa Fig 6 Ref T1-0), and the drain or the source of the selection transistor is connected to the anode or the cathode shared by the plurality of fuse elements (see Ashizawa Fig 6 Ref T1-0).
As to claim 4, Ashizawa discloses the semiconductor device according to claim 2, wherein
the plurality of fuse elements include: a gate wiring (see annotated image of Ashizawa Fig 6 below) including the filament of each of the fuse elements; and a plurality of wirings (see annotated image of Ashizawa Fig 6 below) configured to form the anode of each of the fuse elements and the cathode shared by the plurality of fuse elements or to form the cathode of each of the fuse elements and the anode shared by the plurality of fuse elements.
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As to claim 9, Ashizawa discloses the semiconductor device according to claim 1, wherein
the plurality of fuse elements are electrical fuse elements (see Ashizawa Para [0005]) each of which resistance is changed by application of a voltage (see Ashizawa Paras [0040] and [0041]).
As to claim 10, Ashizawa discloses the semiconductor device according to claim 9, wherein
the plurality of fuse elements are electrical fuse elements (see Ashizawa Para [0005]) in which electromigration is caused by application of a voltage (see Ashizawa Paras [0040] and [0041).
As to claim 11, Ashizawa discloses the semiconductor device according to claim 9, wherein
the selection element is a selection transistor (see Ashizawa Fig 6 Ref T1-0) that switches the plurality of fuse elements to a voltage application target and a voltage non-application target (see Ashizawa Paras [0040] and [0041]).
As to claim 12, Ashizawa discloses the semiconductor device according to claim 1, further comprising
a cell array (see Ashizawa Fig 6 Refs FA0-FB(n-1)) having a plurality of cells (see Ashizawa Para [0031]), wherein
the plurality of cells each include the fuse element, and share the selection element (see Ashizawa Fig 6 Ref T1-0).
As to claim 13, Ashizawa discloses an electronic apparatus (see Ashizawa Para [0029]) comprising a semiconductor device (see Ashizawa Fig 6), wherein
the semiconductor device includes: a plurality of fuse elements (see Ashizawa Fig 6 Refs FA0 and FB0); and a selection element (see Ashizawa Fig 6 Ref T1-0) that is provided in common (see Ashizawa Fig 6 the node left for Ref INV0) to the plurality of fuse elements and switches the plurality of fuse elements between a conduction target and a non-conduction target (see Ashizawa Paras [0040] and [0041]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ashizawa, US 20070230079 A1 in view of Kanda, US 20120243289 A1
As to claim 5, Ashizawa discloses the semiconductor device according to claim 4, wherein
the gate wiring is formed in a shape (see annotated image of Ashizawa Fig 6 above).
Ashizawa does not appear to disclose a shape in which a line width of each of the fuse elements other than the filament is larger than a line width of the filament of each of the fuse elements.
Kanda discloses a shape (see Kanda Fig 19 Ref 113) in which a line width of each of the fuse elements other than the filament is larger than (see Kanda Para [0160]) a line width of the filament of each of the fuse elements (see Kanda Fig 19 Ref 1).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a semiconductor device, as disclosed by Ashizawa, may implement particular wiring layouts, as disclosed by Kanda. The inventions are well known variants of layouts for fuse circuits and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Kanda’s attempt to control voltage drop in fuse circuits (see Kanda Para [0160]).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ashizawa, US 20070230079 A1, in view of Noguchi, US 20210272642 A1.
As to claim 8, Ashizawa discloses the semiconductor device according to claim 1, wherein
the plurality of fuse elements are formed in a silicide structure.
Ashizawa does not appear to explicitly disclose a High-k Metal Gate (HKMG) structure.
Noguchi discloses a High-k Metal Gate (HKMG) structure (see Noguchi Paras [0028] and [0029]).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a semiconductor device, as disclosed by Ashizawa, may implement particular fuses, as disclosed by Noguchi. The inventions are well known variants of layouts for fuse circuits and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Noguchi’s attempt to better control for currents during fuse setting (see Noguchi Para [0016]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Takaoka, US 20180005704 A1 discloses a High-k Metal Gate (HKMG) structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEROME LARRY LEBOEUF whose telephone number is (571)272-7612. The examiner can normally be reached M-Th: 8:00AM - 6:00PM EST.
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/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 09/16/2026
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