Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Amendment
The amendment filed on 08/25/2026 has been entered into this application. Claims 5-6 and 10-13 are cancelled.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, and 14-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kino et al. (20230097485 A1, previously cited reference).
Regarding claim 1, Kino discloses a comparator (51) (figs. 3, 4, 10B) that compares a signal with a reference signal and outputs a comparison result, the comparator (51) comprising: a differential circuit that outputs a differential voltage between the signal and the reference signal [pars. 0138-141]; and
an active load circuit (PT11, PT12) electrically connected to the differential circuit,
wherein the differential circuit includes first and second transistors (NT11, NT12) provided on a surface of a substrate a semiconductor substrate [par. 0188], and the first and second transistors have channel regions extending in a direction substantially perpendicular to the surface of the substrate the semiconductor substrate, as can be seen in depicted drawing (figs. 4 and 10B) [pars. 0139-141],
depicted drawing (fig. 4) described a configuration corresponding to wherein the active load circuit includes third and fourth transistors (PT11, PT12) provided on the surface of the substrate, the first and second transistors (NT11, NT12) are n-type transistors,
the third and fourth transistors are p-type transistors (fig. 19), and
gate insulating films (127) of the third and fourth transistors (PT11, PT12) are thicker than gate insulating films (127) of the first and second transistors (NT11, NT12) [pars. 0173-176].
For the purposes of clarity, thickness considering the BRI consistent with instant disclosure is the dimensions and measurements of depth, width, breadth, or size. In another word thickness is the measure of an object's width, depth or breadth· The state or quality of having a large depth, width or breadth. Width, depth, breadth or size comparative is the state of “thicker than”. Further, thickness/thicker than is considered as the measure of an object's width, depth or breadth or size. The state or quality of having a large depth, width or breadth or size.
As to claims 2-3, Kino also discloses a structure that is use in a comparator system that is implementing limitations such as, wherein depicted drawing (fig. 10B) described a configuration corresponding to the channel region wherein the channel/trench regions of the first and second transistors have an uneven shape along a direction substantially perpendicular to a channel length direction, as can be seen in depicted drawing (fig. 10B) [par.0194] (claim 2); and depicted drawing (fig. 6B) described a configuration corresponding to the channel region wherein the channel/trench regions of the first and second transistors (NT11, NT12) do not have an uneven shape along the channel length direction as can be seen in depicted drawing (fig. 6B) (claim 3).
As to claim 4, Kino also disclose depicted drawing (fig. 4 and 10B) described a configuration corresponding to wherein the active load circuit includes third and fourth transistors (PT11, PT12) provided on the surface of the substrate, and channel regions of the third and fourth transistor (PT11, PT12) shave an uneven shape along a channel length direction [pars. 0179-181].
As to claim 14, Kino also discloses, depicted drawing (figs. 3, 4 and 10B) that described a configuration corresponding to the light detection element comprising:
a pixel portion (11) including a photoelectric conversion element that photoelectrically converts incident light into a pixel signal; and a comparator (51) that compares the pixel signal with a reference signal and outputs a comparison result, the comparator including: a differential circuit that outputs a differential voltage between the pixel signal and the reference signal; and an active load circuit (PT11, PT12) electrically connected to the differential circuit, wherein the differential circuit includes first and second transistors (NT11, NT12) provided on a surface of a substrate, and the first and second transistors have channel regions (see fig. 10B) extending in a direction substantially perpendicular to the surface of the substrate the semiconductor substrate, as can be seen in depicted drawing (figs. 4 and 10B) [pars. 0139-141].
As to claim 15, Kino also disclose depicted drawing (fig. 20) described a configuration corresponding to the, wherein the pixel portion (11) is provided on a first substrate, the comparator (51) is provided on a second substrate different from the first substrate, the first substrate and the second substrate are laminated, and the pixel portion pixel array part 11 and the comparator (51) are electrically connected by a through electrode provided on the first or second substrate or a wiring junction between a wiring of the first substrate and a wiring of the second substrate [pars. 0095, 0210, 0236-0237].
As to claims 16 and 19, Kino also discloses a structure that is use in a comparator system that is implementing limitations such as, wherein the pixel portion pixel array part 11 and the comparator (51) are provided on the same first substrate semiconductor substrates (chips), the comparator (51) is provided above the pixel portion of the first substrate, and the pixel portion and the comparator are electrically connected by a contact plug provided in an interlayer insulating film between the pixel portion and the comparator [pars. 0235-240], as can be seen in depicted drawing (fig. 20) (claim 16); wherein the pixel portion pixel array part 11 and the comparator (51) are provided on the same first substrate, the differential circuit is provided in a same layer as a transistor of the pixel portion, the active load circuit is provided above the pixel portion of the first substrate [pars. 0128-140], and the differential circuit and the active load circuit are electrically connected by a contact plug provided in an interlayer insulating film between the differential circuit and the active load circuit [pars. 0235-240], as can be seen in depicted drawing (fig. 20) (claim 19).
For the purposes of clarity, first and second considered arbitrary.
As to claims 17 and 18, Kino also discloses a structure that is use in a comparator system that is implementing limitations such as, wherein the differential circuit is provided on a first substrate [pars. 0133, 0152], depicted drawing (fig. 4 and 6B) described a configuration corresponding to the active load circuit is provided on a second substrate different from the first substrate, the first substrate and the second substrate are laminated, and the differential circuit and the active load circuit are electrically connected by bonding a wiring of the first substrate and a wiring of the second substrate [pars. 0095, 0210, 0236-0237] (claim 17); and wherein the pixel portion pixel array part 11 and the differential circuit [pars. 0133, 0152] are provided on the same first substrate, the differential circuit is provided above the pixel portion of the first substrate, and the pixel portion pixel array part 11 and the differential circuit are electrically connected by a contact plug provided in an interlayer insulating film between the pixel portion and the differential circuit [pars. 0095, 0210, 0236-0237] (claim 18).
As to claim 20, Kino also discloses depicted drawing (fig. 20) described a configuration corresponding to the electronic device comprising the light detection element [pars. 0255-260].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kino et al. (20230097485 A1, previously cited reference) in view of Yamakawa (20220302192 A1, previously cited reference)
As to claims 7-9, Kino teaches of the features of claims 7-9, as applied to claim 1, comprising an active load circuit (PT11, PT12) electrically connected to the differential circuit, wherein the differential circuit includes first and second transistors (NT11, NT12) provided on a surface of a substrate a semiconductor substrate [par. 0188], and the first and second transistors have channel regions extending in a direction substantially perpendicular to the surface of the substrate the semiconductor substrate, as can be seen in depicted drawing (figs. 4 and 10B) [pars. 0139-141].
Kino fail to teach the constructional changes in the device/system of claim 1, as that claimed by Applicants claims 7-9, such as, wherein channel length directions of the third and fourth transistors are substantially perpendicular or substantially parallel to a (100) crystal plane of the substrate (claim 7); wherein the substrate is a 45 degree notch substrate, and channel length directions of the third and fourth transistors are substantially perpendicular or substantially parallel to a notch plane on the surface of the substrate (claim 8); and wherein the substrate is a 0 degree notch substrate, and channel length directions of the third and fourth transistors are directions inclined at about 45 degrees or about 135 degrees with respect to a notch plane on the surface of the substrate (claim 9);
However, even though, Kino fail to teaches the constructional/structural change differences as that claimed by Applicants claims 7-9, the constructional changes differences are considered obvious design adjustment and variation in view of the field of comparators having transistors, a configuration in which channel length direction of the transistors is substantially parallel to the crystal surface or notch surface, is known, as evidence by Yamakawa (Yamakawa, as can be seen in depicted (figs. 8 and 16).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify Kino with the constructional/structural change differences as that claimed by Applicants claims 7-9 in the manner set forth in applicant's claims, in order to manufacture an imaging device, and in order to provide an imaging device in which noise can be reduced, since it has been held that the provision of adjustability, where needed, involves only routine skill in the art, In re Stevens, 101 USPQ 284 (CC1954).
Response to Arguments
Applicant’s arguments/remarks, (see pages 6-9), filed on 08/25/2026, with respect to the rejection(s) of claim(s) have been fully considered but are not persuasive.
Applicant’s arguments:
a) Applicant argues that Kino fails to disclose various features recited in Applicant's claim 1. For example, Kino does not disclose first and second transistors of the differential circuit that are n-type transistors having channel regions extending in a direction substantially perpendicular to the surface of the substrate, third and fourth transistors of the active load circuit that are p-type transistors, and gate insulating films of the third and fourth transistors that are thicker than gate insulating films of the first and second transistors.
Examiner's response:
With respect to argument (a), it is respectfully pointed out to applicant that this argument is not persuasive because the newly amended independent claims 1 and 14 limitations is identical/similar to the claims 5 and 6 of the previously presented claims 5 and 6. Previously claims 5 and 6 was rejected under 35 U.S.C. 102 as being anticipated by Kino. Therefore, it is respectfully pointed out to applicant that this argument is not persuasive because the Applicant has not provided any arguments or case that the rejection of the claims are not anticipated or that has not been established as rejected in the previous Official Action, since the limitations in review appears to be well known and expressly disclosed in the art Kino. It is respectfully pointed out to applicants that this argument is not persuasive because it is noted that by applicant's own account (applicant argument, page 7, paragraphs 2 and 3) the cited reference Kino discloses attributes transistor performance characteristics to differing transistor structures, including W-extension and L-extension transistor configurations.
It is respectfully pointed out to applicants that it has been held that during examination See In re Zletz, 893 F.2d 319, 321, 13 USPQ2d 1320, 1322 (Fed. Cir. 1989) ("During patent examination the pending claims must be interpreted as broadly as their terms reasonably allow."); and further, Applicant is reminded that, during examination proceedings, claims are given their broadest reasonable interpretation and a claim must be read in accordance with the percepts of English grammar and words should be given their plain, ordinary meaning. In re Hyatt, 708 F2d 712, 218 USPQ 195 (Fed. Cir. 1983). In this case, thicker considering the BRI consistent with instant disclosure is the dimensions and measurements of depth, width, breadth, or size comparable. In another word thicker/thickness is the measure of an object's width, depth or breadth· The state or quality of having a large depth, width or breadth. Width, depth, breadth or size in comparative, as such, it is respectfully pointed out to applicant that this argument is not persuasive since the scope of the claim limitations “thicker” being argue would include the measure of width, depth, breadth or size considering the broadest reasonable interpretation consistent with the instant disclosure.
Further, it is respectfully pointed out to applicant that this argument is not persuasive because Kino also discloses (see abstract) [pars. 0052, 0084-85] general constructure/structure of the transistor(s), the transistor(s) (first, second, third, fourth……or more) of the type (i.e. n-type or p-type) has/having a three-dimensional structure including a channel parallel to or perpendicular to a direction of a current flow that anticipates “first and second transistors of the differential circuit that are n-type transistors having channel regions extending in a direction substantially perpendicular to the surface of the substrate, third and fourth transistors of the active load circuit that are p-type transistors,” as claimed.
For the purposes of clarity, Kino discloses [par. 075] that the trench transistors …. have a larger effective channel width for each plane area than the FIN transistor, advantageously increasing an on current that anticipates gate insulating films of the transistors (i.e. third and fourth) that are thicker than gate insulating films of the (i.e. first and second) transistors. Kino discloses [par. 0242] configurations and structures of the imaging device described in the embodiments are merely exemplary and thus can be changed as needed. Considering the BRI extending width, depth, breadth or size corresponded to structure of thicker than as claimed.
In conclusion, Applicant is reminded that the teachings or suggestions of the prior art that have been used as evidence within a rejection of the claimed invention in view of the prior art under 35 U.S.C. 102 or 103, as set forth by the Court, are to be evaluated and determined not just from one or more specifically identified quotes to individual sections of the text of the prior art document but are in fact to be evaluated and determined from all that the prior art document teaches or suggests, In re BODE et al, 193 USPQ 12 at 17 (CCPA, 1977), with some reliance on the knowledge of one of ordinary skill at the time the invention was made in order to provide an enabling disclosure, In re BODE et al, 193 USPQ 12 at 16 (CCPA, 1977). In view of this, then contrary to Applicant’s arguments to the contrary the Examiner’s need not necessarily point to specific sections of the prior art when supporting a rejection of the claimed invention in view of the prior art under 35 U.S.C. 102.
Finally, one of ordinary skill before the effective filing date of the claimed invention and/or at the time the invention was made would have fairly and reasonably recognized that the prior art does properly support a rejection of the claimed invention under 35 U.S.C. 102.
b) Applicant argues that ……… There is no disclosure or suggestion of the relative thicknesses of the gate insulating films of the third and fourth transistors as compared to those of the first and second transistors.
Applicant argues that ……………... the Action does not identify a disclosure in Kino that the gate insulating films of the p-type active load transistors are thicker than the gate insulating films of the n-type differential transistors, as recited in Applicant's claim 1. The cited portions of Kino discuss transistor structures and gate configurations generally, but do not disclose the specific thickness relationships recited in the claim.
Since Kino fails to disclose every limitation of amended claim 1, a prima facie case of anticipation is not presented for the claim. For reasons similar to those provided regarding claim 1, claim 14 is distinct, although each claim must be considered according to its particular recitations.
Applicant also argues that Claims 7-9 and 11-13 were rejected under 35 U.S.C. 103 …... over Kino in view of Yamakawa. This rejection is traversed.
Kino does not disclose the comparator of amended claim 1 for at least the reasons set forth above (argument (a)). ………………………………., Yamakawa does not remedy the deficiencies of Kino with respect to amended claim 1. Yamakawa is ……………………………………. does not cure the absence of the claimed relationship between the n-type differential transistors and the p-type active-load transistors, including the requirement that the gate insulating films of the p-type active-load transistors are thicker than the gate insulating films of the n-type differential transistors. Thus, a prima facie case of obviousness is not presented, notwithstanding the introduction of Yamakawa.
Accordingly, Applicant respectfully requests reconsideration and withdrawal of the rejection under 35 U.S.C. 103. Applicant submits that this application is in condition for allowance, and requests early and favorable action in this regard.
Examiner's response:
With respect to argument (b), it is respectfully pointed out to applicant that for the same reasons as discussed above in relation to argument (a), applicant argument(s) regarding argument(s) (b) is/are not persuasive.
In addition, it is respectfully pointed out to applicant that this/these argument(s) is/are not persuasive because the Applicant have not provided any proof and/or any factual evidence that the claims as recited previously in 5 and 6 are not anticipated. Kino clearly discloses that the gate insulating films of the p-type active load transistors are thicker than in terms of extending width, depth, breadth or size corresponded to structure of thicker than with the application of comparator [par. 0242], comparator a device, circuit, or standard used to measure or judge the differences between two things as claimed, that anticipate measuring whether the gate insulating films of the n-type differential transistors, as recited in Applicant's claim 1, as detailed above. Applicant has not provided any proof and/or any factual evidence that suggest or obviate the examiner's position would not have been anticipated and/or that the claim(s) 1 as rejected is/are not anticipated.
Finally, in response to applicant's arguments with respect to the rejection(s) of claim(s) under 35 U.S.C. 103(a), the examiner did recognize that obviousness can only be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988) and In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992). In this case, since both the instant application as disclosed in (see abstract) [par. 0002, 0006] (figs. 1-3), and cited references are reasonably concerned with the comparator and imaging device/apparatus for semiconductor/image sensor, which the applicant is involved, the cited references are considered as an analogous art. As such, the rejections are proper, and the argument/remarks for request for reconsideration does not appear to place the application in condition for allowance. Therefore, the claims are still rejected as shown in the detail above.
In conclusion, Applicant has argued the patentability of dependent claims, based solely upon the patentability of independent claim(s), and has presented no additional arguments exclusively pertaining to the claims, since the applicant has not argued the examiner’s position about the rejection(s) regarding the dependent claims, in the previous Official action. The applicant has acquiesced.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Isiaka Akanbi whose telephone number is (571) 272-8658. The examiner can normally be reached on 8:00 a.m. - 4:30 p.m.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tarifur R. Chowdhury can be reached on (571) 272-2287. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/ISIAKA O AKANBI/Primary Examiner, Art Unit 2877
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