Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
The information disclosure statement filed on 12/09/2024 has been entered and considered by the examiner.
Drawings
The drawings filed on 12/09/2024, has been accepted for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 10 and 14-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kino et al. (20230097485 A1).
Regarding claim 1, Kino discloses a comparator (51) (figs. 3, 4, 10B) that compares a signal with a reference signal and outputs a comparison result, the comparator (51) comprising: a differential circuit that outputs a differential voltage between the signal and the reference signal [pars. 0138-141]; and
an active load circuit (PT11, PT12) electrically connected to the differential circuit,
wherein the differential circuit includes first and second transistors (NT11, NT12) provided on a surface of a substrate a semiconductor substrate [par. 0188], and the first and second transistors have channel regions extending in a direction substantially perpendicular to the surface of the substrate the semiconductor substrate, as can be seen in depicted drawing (figs. 4 and 10B) [pars. 0139-141].
As to claims 2-3, Kino also discloses a structure that is use in a comparator system that is implementing limitations such as, wherein depicted drawing (fig. 10B) described a configuration corresponding to the channel region wherein the channel/trench regions of the first and second transistors have an uneven shape along a direction substantially perpendicular to a channel length direction, as can be seen in depicted drawing (fig. 10B) [par.0194] (claim 2); and depicted drawing (fig. 6B) described a configuration corresponding to the channel region wherein the channel/trench regions of the first and second transistors (NT11, NT12) do not have an uneven shape along the channel length direction as can be seen in depicted drawing (fig. 6B) (claim 3).
As to claim 4, Kino also disclose depicted drawing (fig. 4 and 10B) described a configuration corresponding to wherein the active load circuit includes third and fourth transistors (PT11, PT12) provided on the surface of the substrate, and channel regions of the third and fourth transistor (PT11, PT12) shave an uneven shape along a channel length direction [pars. 0179-181].
As to claims 5 and 6, Kino also disclose, depicted drawing (fig. 4 and 6B) described a configuration corresponding to wherein the active load circuit includes third and fourth transistors provided on the surface of the substrate, and gate insulating films (127) of the third and fourth transistors (PT11, PT12) are thicker than gate insulating films (127) of the first and fourth transistors [pars. 0173-176] (claim 5); and depicted drawing (fig. 4) described a configuration corresponding to wherein the active load circuit includes third and fourth transistors (PT11, PT12) provided on the surface of the substrate, the first and second transistors (NT11, NT12) are n-type transistors, and the third and fourth transistors are p-type transistors (fig. 19) (claim 6).
As to claim 10, Kino also disclose depicted drawing (fig. 4) described a configuration corresponding to wherein the active load circuit includes third and fourth transistors (PT11, PT12) provided on the surface of the substrate, the first and second transistors are p-type transistors (NT11, NT12), and the third and fourth transistors are n-type transistors (see fig. 19) [pars. 0173-176] [pars. 0228-230].
As to claim 14, Kino also disclose, depicted drawing (figs. 3, 4 and 10B) described a configuration corresponding to the light detection element comprising:
a pixel portion(11) including a photoelectric conversion element that photoelectrically converts incident light into a pixel signal; and a comparator (51) that compares the pixel signal with a reference signal and outputs a comparison result, the comparator including: a differential circuit that outputs a differential voltage between the pixel signal and the reference signal; and an active load circuit (PT11, PT12) electrically connected to the differential circuit, wherein the differential circuit includes first and second transistors (NT11, NT12) provided on a surface of a substrate, and the first and second transistors have channel regions (see fig. 10B) extending in a direction substantially perpendicular to the surface of the substrate the semiconductor substrate, as can be seen in depicted drawing (figs. 4 and 10B) [pars. 0139-141].
As to claim 15, Kino also disclose depicted drawing (fig. 20) described a configuration corresponding to the, wherein the pixel portion (11) is provided on a first substrate, the comparator (51) is provided on a second substrate different from the first substrate, the first substrate and the second substrate are laminated, and the pixel portion pixel array part 11 and the comparator (51) are electrically connected by a through electrode provided on the first or second substrate or a wiring junction between a wiring of the first substrate and a wiring of the second substrate [pars. 0095, 0210, 0236-0237].
As to claims 16 and 19, Kino also discloses a structure that is use in a comparator system that is implementing limitations such as, wherein the pixel portion pixel array part 11 and the comparator (51) are provided on the same first substrate semiconductor substrates (chips), the comparator (51) is provided above the pixel portion of the first substrate, and the pixel portion and the comparator are electrically connected by a contact plug provided in an interlayer insulating film between the pixel portion and the comparator [pars. 0235-240], as can be seen in depicted drawing (fig. 20) (claim 16); wherein the pixel portion pixel array part 11 and the comparator (51) are provided on the same first substrate, the differential circuit is provided in a same layer as a transistor of the pixel portion, the active load circuit is provided above the pixel portion of the first substrate [pars. 0128-140], and the differential circuit and the active load circuit are electrically connected by a contact plug provided in an interlayer insulating film between the differential circuit and the active load circuit [pars. 0235-240], as can be seen in depicted drawing (fig. 20) (claim 19).
For the purposes of clarity, first and second considered arbitrary.
As to claims 17 and 18, Kino also discloses a structure that is use in a comparator system that is implementing limitations such as, wherein the differential circuit is provided on a first substrate [pars. 0133, 0152], depicted drawing (fig. 4 and 6B) described a configuration corresponding to the active load circuit is provided on a second substrate different from the first substrate, the first substrate and the second substrate are laminated, and the differential circuit and the active load circuit are electrically connected by bonding a wiring of the first substrate and a wiring of the second substrate [pars. 0095, 0210, 0236-0237] (claim 17); and wherein the pixel portion pixel array part 11 and the differential circuit [pars. 0133, 0152] are provided on the same first substrate, the differential circuit is provided above the pixel portion of the first substrate, and the pixel portion pixel array part 11 and the differential circuit are electrically connected by a contact plug provided in an interlayer insulating film between the pixel portion and the differential circuit [pars. 0095, 0210, 0236-0237] (claim 18).
As to claim 20, Kino also discloses depicted drawing (fig. 20) described a configuration corresponding to the electronic device comprising the light detection element [pars. 0255-260].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-9 and 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kino et al. (20230097485 A1) in view of Yamakawa (20220302192 A1)
As to claims 7-9 and 11-13, Kino teaches of the features of claims 7-9 and 11-13, as applied to claim 1, comprising an active load circuit (PT11, PT12) electrically connected to the differential circuit, wherein the differential circuit includes first and second transistors (NT11, NT12) provided on a surface of a substrate a semiconductor substrate [par. 0188], and the first and second transistors have channel regions extending in a direction substantially perpendicular to the surface of the substrate the semiconductor substrate, as can be seen in depicted drawing (figs. 4 and 10B) [pars. 0139-141].
Kino fail to teach the constructional changes in the device/system of claim 1, as that claimed by Applicants claims 7-9 and 11-13, such as, wherein channel length directions of the third and fourth transistors are substantially perpendicular or substantially parallel to a (100) crystal plane of the substrate (claim 7); wherein the substrate is a 45 degree notch substrate, and channel length directions of the third and fourth transistors are substantially perpendicular or substantially parallel to a notch plane on the surface of the substrate (claim 8); wherein the substrate is a 0 degree notch substrate, and channel length directions of the third and fourth transistors are directions inclined at about 45 degrees or about 135 degrees with respect to a notch plane on the surface of the substrate (claim 9); wherein channel length directions of the first and second transistors are substantially perpendicular or substantially parallel to a (110) crystal plane of the substrate (claim 11); wherein the substrate is a 45 degree notch substrate, and channel length directions of the first and second transistors are directions inclined at about 45 degrees or about 135 degrees with respect to a notch plane on the surface of the substrate (claim 12); and wherein the substrate is a 0 degree notch substrate, and channel length directions of the first and second transistors are substantially perpendicular or substantially parallel to a notch plane on the surface of the substrate (claim 13).
However, even though, Kino fail to teaches the constructional/structural change differences as that claimed by Applicants claims 7-9 and 11-13, the constructional changes differences are considered obvious design adjustment and variation in view of the field of comparators having transistors, a configuration in which channel length direction of the transistors is substantially parallel to the crystal surface or notch surface, is known, as evidence by Yamakawa (Yamakawa, as can be seen in depicted (figs. 8 and 16).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify Kino with the constructional/structural change differences as that claimed by Applicants claims 7-9 and 11-13 in the manner set forth in applicant's claims, in order to manufacture an imaging device, and in order to provide an imaging device in which noise can be reduced, since it has been held that the provision of adjustability, where needed, involves only routine skill in the art, In re Stevens, 101 USPQ 284 (CC1954).
Additional Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The references listed in the attached form PTO-892 teach of other prior art comparator.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Isiaka Akanbi whose telephone number is (571) 272-8658. The examiner can normally be reached on 8:00 a.m. - 4:30 p.m.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tarifur R. Chowdhury can be reached on (571) 272-2287. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/ISIAKA O AKANBI/Primary Examiner, Art Unit 2877
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