DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/09/2024. The submission is following the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-7, 9 are rejected under 35 U.S.C. 103 as being unpatentable over Mougin et al., (US 2013/0314121 A1) in view of Lewis et al., (US 2020/0303325 A1).
Regarding claim 1, Mougin et al., disclose a sensor fabric for detecting an attack on transistors ([0009], “Some embodiments relate to a method for detecting an attack by laser beam on an electronic microcircuit…the microcircuit comprising a circuit to be protected against attacks”, and [0014], “a microcircuit comprising a circuit to be protected against attacks by laser beam”) comprising: a plurality of sensor clusters, each sensor cluster comprising: a plurality of photodetectors and transistors, each photodetector (PHD)being disposed next to a respective said transistor (MT)(see [0036], “the photodiodes are distributed over the area to be protected according to a matrix configuration, in rows and in columns transversal to the rows”; and Fig.5 shows a photodetector (PHD) is adjacent to/next to a respective said transistor (MT). Indicating that grouping these repetitive photodiodes in rows and columns within a matrix layout is showing the layout of a plurality of sensor clusters);a standard cell comprising a thresholding comparator for ([0030]-[0032], “output of each photodiode PHD, and send it to the comparator CP1”), a first input and a second input being proportional to incident light sensed by the respective photodetectors ([0029]-[0030], “representative of the light intensity received by one of the photodiodes PHD”); an aggregator (OR logic gate and a processing circuit (WB), see [0030]-[0032]) for aggregating the outputs from the clusters to produce an aggregated output, and triggering an alarm on detection of an attack based on the aggregated output ([0032], “The output of each comparator is connected to an input of an OR logic gate…and supplying the detection signal DT”, and the signal DT is received by a processing circuit (WB) configured to take or trigger any appropriate measure in the event of an attack, like erasing one or more memories containing sensitive data, locking or cutting off the power supply, [0030]-[0032])
Mougin et al., does not disclose comparing the first input from a first group of the photodetectors of the respective cluster and the second input from a second group of the photodetectors of the respective cluster, and flipping an output of the standard cell if a difference between the first input and second input exceeds a predetermined threshold as claimed.
Lewis et al., discloses comparing a first input from a first group of the photodetectors of the respective cluster and a second input from a second group of the photodetectors of the respective cluster ([0073], “two inverter chains 805A and 805B, each made up of a chain of detector circuits 805 (similar to detector circuits 300, 400A, 400B, 500, 600), receive the same pulse stream input”), and flipping an output of the standard cell if a difference between the first input and second input exceeds a predetermined threshold ([0073], “if one chain is exposed to incident radiation, altering the propagation delay through one or more stages, a phase difference between the outputs of the inverter chain 805A and 805B will be observable “, or [0076], “During operation, any increase or reduction in delay through either chain (905A or 905B) due to an illumination attack may be detected by the phase detector”). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Mougin et al., by utilizing the teaching of Lewis et al., to improve noise cancellation and prevent false alarms, keeping the security fabric stable and accurate.
Regarding claims 2 and 3, Mougin et al., in view of Lewis et al., as discussed in claim 1, Mougin et al., does not disclose for each cluster, the first group of photodetectors and the second group of photodetectors each comprise half of the photodetectors in the cluster as claimed. Lewis et al., discloses for each cluster, the first group of photodetectors and the second group of photodetectors each comprise half of the photodetectors in the cluster ([0073], “two inverter chains 805A and 805B, each made up of a chain of detector circuits”). Lewis et al., also discloses each photodetector being in exactly one of the first group and second group (Fig.8 and [0073]). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Mougin et al., by utilizing the teaching of Lewis et al., for better noise cancellation.
Regarding claim 5, Mougin et al., in view of Lewis et al., as discussed in claim 1, Mougin et al., discloses each photodetector comprising a reverse-biased pn junction ([0035], “The transistor MT is formed in P-doped well PW, while the photodiode PHD is formed in an N-doped well NW like the P-channel MOS transistors… the photodiode PHD comprises an N+-doped area PD formed in the well NW”).
Regarding claim 6, Mougin et al., in view of Lewis et al., as discussed in claim 1, does not disclose the output using a logic tree as claimed. However, Mougin et al., disclose aggregating outputs from multiple detector channel through logic circuitry (OR logic gate, [0032]), it would have been obvious to one of ordinary skill in the art to implement the aggregation using a logic tree to minimize signal propagation delay. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Mougin et al., in view of Lewis et al., accordingly to improve the signal timing by reducing signal propagation delay.
Regarding claim 7, Mougin et al., in view of Lewis et al., as discussed in claim 1, Mougin et al., disclose that the aggregator: keeps a count of each occasion the aggregated output indicates an attack ([0034], “The detection signal DT can also indicate numbers of photodiodes having supplied a light intensity signal lower than the threshold value Vr1, ranging between the threshold values Vr1 and Vr2, and above the threshold value Vr2”); and triggers the alarm if the count exceeds a predetermined threshold ([0034], ‘Therefore, the circuit WB can select a protective measure according to the signals supplied by the two comparators CP1, CP2’, and [0030], “The circuit WB can also be configured to take or trigger any appropriate measure in the event of an attack”).
Regarding claim 9, Mougin et al., in view of Lewis et al., as discussed in claim 1, Mougin et al., disclose a spacing between nearest ones of the photodetectors being defined based on a predetermined laser spot size ([0036], “shown in FIG. 6, the photodiodes are distributed over the area to be protected according to a matrix configuration… By choosing a sufficiently small mesh width for the network PGA, a selective attack of a part of the area A3 can be made impossible without a photodiode of the network PGA detecting the presence of a laser beam”).
5. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Mougin et al., in view of Lewis et al., and further in view of Valentian (US 2008/0136505 A1).
Regarding claim 4, Mougin et al., in view of Lewis et al., as discussed in claim 1, does not disclose the thresholding comparator being biased with the leakage current of another transistor as claimed. Valentian discloses a thresholding comparator ([0034], “a circuit for comparing the leakage currents of the two transistors” and [0036], “The circuit for comparing currents preferably emits a brief pulse on a first output if the current on a first input is higher than on the second”) being biased with the leakage current of another transistor ([0038], “the first reference transistor, which is a global leakage current of type ISTH+IGIDL, while the second input receives a leakage current which does not comprise any component ISTH because the source and the drain of the second reference transistor”). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Mougin et al., and Lewis et al., by utilizing the teaching of Valentian, to improve signal to noise margin for the attack detection.
6. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Mougin et al., in view of Lewis et al., and further in view of Nicol (US 2020/0167309 A1).
Regarding claim 8, Mougin et al., in view of Lewis et al., as discussed in claim 1, do not disclose the aggregator aggregating the outputs based on spatial proximity of the respective cluster as claimed. Nicol discloses an aggregator aggregating the outputs ([0037], “A spatial routing can include interconnection paths, which can be used for communicating between or among processing elements, clusters… The latency-aware data transfer can minimize latency by reducing a number of switching elements, length of interconnects”) based on spatial proximity of the respective cluster ([0043], “the locations of the allocated clusters within the reconfigurable fabric, adjacencies of allocated clusters”). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Mougin et al., and Lewis et al., by utilizing the teaching of Nicol, to minimize transmission latency (Nicol, [0037]).
Allowable Subject Matter
7. Claims 10, 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 10, the prior art fails to disclose the spacing comprising placing a photodetector every Ngate pitch gate pitches from a centre of a said transistor footprint such that:
Ngate pitch -wiaser / CGP = 1.7 - FWHM / CGP, where WIaseris the laser spot width, CGP is a contacted gate pitck pitch and FWHM is a full-width at half-maximum power.
Regarding claim 11, the prior art fails to disclose inserting one or more dummy transistors for each photodetector, to maintain a geometry of the respective group of the photodetectors.
Conclusion
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/M.T.T./Examiner, Art Unit 2878
/GEORGIA Y EPPS/Supervisory Patent Examiner, Art Unit 2878
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