DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-2, 4, 12, 19, 21, 24, 26, 30-31, 33, 37-39, 41, 45-46, 48, and 52-53 are rejected, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention.
For claims 1, 4, 12, 31, 39, and 46, the term “said first BIST” is indefinite because earlier in the claim at least one BIST was declared and so it is unclear to which BIST the claim refers to if there is more than one. It is suggested claims be amended to “…and/or a first Built-In Self-Test (BIST) out of at least one
For claims 1, 4, 31, 39, and 46, the term “at least one said first POST” and “said first POST” are indefinite because earlier in the claim at least one POST was declared and so it is unclear to which POST the claim refers to if there is more than one. It is suggested claims be amended to “said at least one
For claims 2, 4, 19, 21, 24, 31, and 46, the term “the second processor” is indefinite because earlier in independent claim at least one second processor was declared and so it is unclear to which second processor the claim refers to if there is more than one. It is suggested independent claim 1 be amended to “to a second processor out of at least one second processor; and the second processor that is adapted to” and claims 31 and 46 be amended to “to a second processor out of at least one second processor”.
For claims 2, 4, 12, 19, 21, 26, 31, 33, 41, 46, and 48, the term “the first processor” and “the first processor core” is indefinite because earlier in independent claim at least one first processor was declared and so it is unclear to which first processor the claim refers to if there is more than one. It is suggested the claim be amended to “the at least one first processor”.
For claims 2 and 4, the term “the comparison” is indefinite because earlier in independent claims multiple comparisons were declared (in claim 1 compare the first data and another 2 compare in the instant claim) and so it is unclear to which the claim refers to. It is suggested the claim be amended to “the ??? comparison”.
For claim 4, the term “the received data” is indefinite because earlier in the claim two received data were declared and so it is unclear to which the claim refers to. It is suggested the claim be amended to “the BIST received data”.
For claims 26, 33, 41, and 48, the term “the first monitoring process” is indefinite because earlier in claim 1/31/39/46, at least one first monitoring process” was declared and so it is unclear to which the claim refers to. It is suggested the claim be amended to “the at least one first monitoring process”.
For claims 26, 33, 41, and 48, the term “the Process Safety Time” lacks sufficient antecedent basis in the claim. It is suggested the claim be amended to “[[the]] a Process Safety Time”.
Dependent claims inherit rejections.
Allowable Subject Matter
Claims 2,4, 19, 21, 30, 37, 45, and 52 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and all 35 USC § 112 rejections are overcome, and no significant change of scope is made.
Reasons for Allowability
The following are reasons for allowance for claims:
For dependent claim 2, Gendler does not teach testing reciprocity between core and PCU and no art was found to teach BIST or POST reciprocity between processors.
For dependent claim 4, Gendler nor other art teaches BIST triggered by POST, in the manner claimed.
For dependent claims 19 and 21, Gendler nor other art teaches determine out of sequence self-tests or test at a wrong time in a manner that would motivate a person of ordinary skill in the art to combine it as an obvious inclusion
For dependent claims 30, 37, 45, and 52, Gendler nor other art teaches specific 100ms time limit in a manner that would motivate a person of ordinary skill in the art to combine it as an obvious inclusion.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 12, 24, 26, 31, 33, 38-39, 41, 46, 48, and 53 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gendler (US 2018/0336111 A1).
For claim 1, Gendler teaches a time-triggered computer system comprising: at least one first processor that is adapted to: perform at least one first monitoring process for monitoring that the at least one first processor is operating correctly; and perform at least one first Power-On Self-Test, POST, and/or at least one first Built-In Self-Test, BIST on the at least one first monitoring process (see figure 1 and other locations: view system 110, including a multi core processor, as said computer system; see [0129], [0131], and other locations: a scheduler starts the test function; scheduling uses T1 and T2; view that as said time triggered; see abstract, [0023], [0120], and other locations: multiple monitoring processes including self-testing; see [0029], [0043], and other locations: tests by core are BIST; tests by OS are POST); and transmit first data, that is indicative of results of at least one said first POST and/or said first BIST, to at least one second processor (see [0028], [0039], [0110], [0121], [0141], and other locations: PCU could be a processor itself; PCU tests core; PCUs include self-test control fore cores; PMA sends results to PCU); and at least one second processor that is adapted to: compare the first data with second data, that is data indicative of expected results from at least one said first POST and/or said first BIST (see [00141] and other locations: testing always involves comparing to predetermined results); and responsive to the comparison, determine if at least one said first POST and/or first BIST has passed or failed (see [0141] and other locations).
For claim 12, Gendler teaches the limitations of claim 1 for the reasons above and further teaches the first processor is further adapted to: perform at least one said first BIST without performing a processor reset (see [0125] and other locations: not all self-tests are reset type).
For claim 24, Gendler teaches the limitations of claim 1 for the reasons above and further teaches the second processor is further adapted to: perform at least one said second BIST without performing a processor reset (see rejection to claim 12).
For claim 26, Gendler teaches the limitations of claim 1 for the reasons above and further teaches the first processor is further adapted to: perform a plurality of first BISTs on the first monitoring process; wherein a sequence of first BISTs and a time interval between respective first BISTs performed on the first monitoring process is predetermined; and optionally: perform said plurality of first BISTs on the first monitoring process within a predetermined time period; and perform said first monitoring process within the predetermined time period, (see rejection to claim 12) wherein the predetermined time period is the Process Safety Time or Fault Tolerant Time Interval (see [0143] and other locations).
For claim 31, the claim recites essentially similar limitations from claim 1. Claim 31 is a method.
For claim 33, Gendler teaches the limitations of claim 31 for the reasons above. The claim recites essentially similar limitations from the combination of claims 1 and 28.
For claims 38 and 53, the claim recites essentially similar limitations as claim 31 and 46 respectively. Claims 38 and 53 are a medium.
For claim 39, the claim recites essentially similar limitations from claim 1.
For claim 41, Gendler teaches the limitations of claim 39 for the reasons above. The claim recites essentially similar limitations from claim 26.
For claim 46, The claim recites essentially similar limitations from claim 31.
For claim 48, Gendler teaches the limitations of claim 46 for the reasons above. The claim recites essentially similar limitations from claim 26.
Conclusion
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/YAIR LEIBOVICH/Primary Examiner, Art Unit 2114