DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to an application filed on 12/19/2024.
Claims 1-20 are pending for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, 10-16 and 18-20 rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Kanzaki et al. (US 2014/0095005 A1 and Kanzaki hereinafter).
As to Claim 1, Kanzaki in its teachings as shown in Fig.1-7 disclose an active discharge method, comprising:
providing an inverter circuit (140) including a plurality of inverter legs including a first inverter leg and a second inverter leg (141, 142), each leg including first and second power switches (Q3 & Q4 of 141; Q5 & Q6 of 142);
in response to a first active discharge event, operating the first and second power switches of the first inverter leg (141) to discharge a high voltage bus (PL2) connected to the inverter (see: U-phase arm and also [0069] - [0074]); and
in response to a second active discharge event, operating the first and second power switches of the second inverter leg (142) to discharge the high voltage bus connected to the inverter (see: V-phase arm and also [0069] - [0076]).
As to Claim 2, Kanzaki disclose the method of claim 1, wherein the plurality of inverter legs further includes a third inverter leg (143), the method further comprising: in response to a third active discharge event, operating the first and second power switches of the third inverter leg to discharge the high voltage bus connected to the inverter (see: W-phase arm and also [0069]- [0076]).
As to Claim 3, Kanzaki disclose the method of claim 2, further comprising: in response to a fourth active discharge event, operating the first and second power switches of the first inverter leg to discharge the high voltage bus connected to the inverter (see [0085]).
As to Claim 4, Kanzaki disclose the method of claim 1, wherein discharging the high voltage bus connected to the inverter includes discharging a high voltage DC bus capacitor connected to the inverter (see C2 and [0046]).
As to Claim 5, Kanzaki disclose the method of claim 1, wherein operating the first and second power switches of the first inverter leg includes maintaining the first power switch on while applying a pulse width modulated signal to the second power switch of the first inverter leg (see [0069], [0071] – [0072] and [0074] – [0076]).
As to Claim 6, Kanzaki disclose the method of claim 5, wherein the PWM signal is determined based on a gate to source voltage of the first one of the power switches (implicit features of semiconductors (MOSFET/IGBT) and see also (Q3-Q8) of Fig.3).
As to Claim 7, Kanzaki disclose the method of claim 1, wherein the first active discharge event includes an internal fault (see Collision: [0080]).
As to Claim 8, Kanzaki disclose the method of claim 1, wherein the first active discharge event includes an ignition off condition (see at the ending process when a running end operation of the vehicle is performed by the user and [0064]).
As to Claim 10, Kanzaki disclose the method of claim 1, wherein operating the first and second power switches of the first inverter leg to discharge the high voltage bus connected to the inverter includes comparing a voltage level of the high voltage bus to a predetermined voltage level (see (S140) and [0085] – [0087]).
As to Claim 11, Kanzaki disclose the method of claim 1, wherein operating the first and second power switches of the first inverter leg to discharge the high voltage bus connected to the inverter includes comparing a temperature of at least one of the first and or second switches to a predetermined temperature (see [0013] and [0075]).
As to Claim 12, Kanzaki in its teachings as shown in Fig.1-7 disclose a high voltage DC active discharge system (160,170), comprising:
a DC power source (110) connected between first and second power rails (PL2, NL1);
a DC bus capacitor (C2) connected between the first and second power rails (PL2, NL1);
an inverter circuit (140) including a first inverter leg (141), a second inverter leg (142) and a third inverter leg (143), each of the first, second and third inverter legs (Q3, Q5, Q7) including first and second power switches (Q2, Q4, Q6) connected in series between the first and second power rails (PL2, NL1);
a controller (160, 170 via 171,172,173) configured to selectively operate the first and second power switches of the first, second and third inverter legs to energize windings of a motor (150) (see [0069] – [0071]); and
wherein the controller is further configured to operate the first and second power switches of a selected one of the first, second or third inverter legs in response to a first active discharge event to discharge the DC bus capacitor (see Fig.5, S100 and also [0063] – [0065], [0069], [0071] – [0072] and [0074] – [0076]).
As to Claim 13, Kanzaki disclose the system of claim 12, wherein the inverter circuit further includes plurality of gate drivers, each of the first and second switches of the first, second and third inverter legs having a corresponding gate driver connected thereto (see (172): [0071] and [0076]).
As to Claim 14, Kanzaki disclose the system of claim 13, wherein gate drivers are configured to selectively operate their respective first and second switches in an on mode, an off mode, and a PWM mode (the implicit operation of a switch and see also [0071] and [0076]).
As to Claim 15, Kanzaki disclose the system of claim 14, wherein gate drivers are configured to selectively the first switch of the first inverter leg in the on mode and the second switch of the first inverter leg in the PWM mode to actively discharge the DC bus capacitor in response to response to the first active discharge event (see [0069], [0071] – [0072] and [0074] – [0076]).
As to Claim 16, Kanzaki disclose the system of claim 15, wherein gate drivers are configured to selectively the first switch of the second inverter leg in the on mode and the second switch of the second inverter leg in the PWM mode to actively discharge the DC bus capacitor in response to response to a second active discharge event (see [0069] – [0076]).
As to Claim 18, Kanzaki in its teachings as shown in Fig.1-7 disclose an inverter circuit (140), comprising:
a first inverter leg (141) including first and second power switches (Q3, Q4) connected in series between first and second power rails (PL2, NL1);
a second inverter leg (142) including first and second power switches (Q5, Q6) connected in series between the first and second power rails (PL2, NL1);
a third inverter leg (143) including first and second power switches (Q7, Q8) connected in series between the first and second power rails (PL2, NL1);
a controller (160, 170 via 171,172,173) configured to selectively operate the first and second power switches of the first, second and third inverter legs to energize windings of a motor (150) (see [0069] – [0071]); and
wherein the controller is further configured to select one of the first, second or third inverter legs based on a predetermined parameter, and operate the first and second switches of the selected inverter leg to actively discharge a DC bus capacitor (C2) connected between the first and second power rails response to a first active discharge event (see Fig.5, S100 and also [0063] – [0065], [0069], [0071] – [0072] and [0074] – [0076]).
As to Claim 19, Kanzaki disclose the inverter circuit of claim 18, wherein the predetermined parameter includes a voltage level of the selected inverter leg (see [0073]).
As to Claim 20, Kanzaki disclose the inverter circuit of claim 18, wherein the predetermined parameter includes a temperature of the first and second power switches of the selected inverter leg (see [0013] and [0075]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 9 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kanzaki in view of Yang et al. (US 2018/0079315 A1 and yang hereinafter).
As to Claim 9, Kanzaki disclose the method of claim 1, however, it doesn’t explicitly disclose:
wherein each inverter leg includes first and second gate drivers connected to the respective first and second power switches, the method further comprising: in response to determining a fault in at least one of the first and/or second gate drivers of the first one of the inverter legs, maintaining the first and second power switches of the first inverter leg on while applying a pulse width modulated (PWM) signal to at least one of the first and/or second power switches of the second inverter leg to discharge the high voltage bus
Nonethless, Yang in its teachings as shown in Fig.1-11 disclose that a phase leg 60 adapted to discharge a link capacitor according to one embodiment of the invention. Upper and lower switching devices 61 and 62 are coupled across the link capacitor (not shown) with a junction between switches switching devices 61 and 62 configured to be coupled to the output load. Switching devices 61 and 62 are coupled to gate drivers 63 and 64 respectively in a conventional manner. Collectively with a controller 65, the gate drivers are configured to discharge the link capacitor by simultaneously activating switching devices 61 and 62 into transitional states (i.e., at less than their full ON states) whenever a discharge event is detected in which the main buses are decoupled from the main DC power source by opening of the contactor switches. (see [0030])
Therefore, it would have been an obvious modification before the effective filing date of the instant application for the gate drivers to discharge the link capacitor by simultaneously activating switching devices into transitional states whenever a discharge event is detected as thought by Yang within the teachings of Kanzaki in order to safely dissipate the charge stored on the link capacitor and to prevent the buildup of temperatures that could damage devices (see also [0030]).
As to Claim 17, Kanzaki disclose the system of claim 15, however, it doesn’t explicitly disclose:
wherein gate drivers are configured to clamp a PWM signal based on a threshold voltage of the first and second power switches
Nonethless, Yang in its teachings as shown in Fig.1-11 disclose that Fig. 11 shows regular PWM gate signals 85 having a full amplitude configured to drive the switching devices to their ON states. In example A, a pulsed gate signal 86 has a reduced amplitude that (when simultaneously provided to both devices in the phase leg) provides a limited current through the phase leg to discharge the link capacitor. If the pulse repetition frequency in Example A would generate a device temperature greater than a specified temperature, then the pulse repetition frequency could be decreases as shown by gate signal 87 in Example B (see [0035])
Therefore, it would have been an obvious modification before the effective filing date of the instant application for gate drivers to clamp a PWM signal based on a threshold voltage of the first and second power switches as thought by Yang within the teachings of Kanzaki in order to safeguard the power switch and improve system efficiency and reliability.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure (us 2011/0133546 A1: Systems and methods are provided for discharging a voltage bus. An electrical system comprises a first switch coupled to a first voltage rail, a second switch coupled between the first switch and a second voltage rail, and a control system coupled to the first switch and the second switch. The control system is configured to alternately activate the first switch and the second switch such that an energy potential between the first voltage rail and the second voltage rail is dissipated through the first switch and the second switch – see [Abstract]).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GABRIEL T AGARED whose telephone number is (571)270-1981. The examiner can normally be reached 8-5 (Mon- Thur).
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/GABRIEL AGARED/ Primary Examiner, Art Unit 2837
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