Prosecution Insights
Last updated: July 17, 2026
Application No. 18/878,525

VOLTAGE MANAGEMENT CIRCUIT

Non-Final OA §102§103§112
Filed
Dec 23, 2024
Priority
Jun 22, 2022 — provisional 63/354,575 +1 more
Examiner
HOANG, HUAN
Art Unit
2827
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Silvaco Inc.
OA Round
1 (Non-Final)
93%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allowance Rate
1141 granted / 1224 resolved
+25.2% vs TC avg
Moderate +6% lift
Without
With
+5.6%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 8m
Avg Prosecution
15 currently pending
Career history
1241
Total Applications
across all art units

Statute-Specific Performance

§101
1.9%
-38.1% vs TC avg
§103
40.9%
+0.9% vs TC avg
§102
27.7%
-12.3% vs TC avg
§112
9.4%
-30.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1224 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 3-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The use of abbreviation “VT” in “a low VT inverter”, “a high VT PMOS” and “a high VT NMOS” in claims 3-6 is unclear and the abbreviation “VT” should be a word. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 2, 8 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kumar et al. (US 2020/0327927, hereinafter “Kumar”). Regarding claim 1, Kumar (Fig. 4) shows an integrated circuit system (memory device 50a) for management of process corners comprising: an electronic device (71), the electronic device having one or more transistors (Fig. 1); and a voltage management circuit (60), the voltage management circuit electrically coupled to the electronic device and having one or more transistors (62 and 63) configured to manage a behavior of a voltage of the electronic device (paragraph [0047]). Regarding claim 8, Kumar (Fig. 4A) shows the integrated circuit system of claim 1, wherein the electronic device comprises a memory (71). Regarding claim 9, Kumar (Fig. 4A) shows the integrated circuit system of claim 8, wherein the memory comprises an SRAM memory (71, SRAM core). Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Poon et al. (US 2006/0072258, hereinafter “Poon”). Regarding claim 1, Poon discloses an integrated circuit system (paragraphs [0001 and [0002]) for management of process corners comprising: an electronic device (Fig. 1, 18), the electronic device having one or more transistors (paragraphs [0005] and [0006]); and a voltage management circuit (Figs. 1 and 5, ESD device 100), the voltage management circuit electrically coupled to the electronic device and having one or more transistors (Fig. 5, clamp circuit 100 comprising transistors 130-172) configured to manage a behavior of a voltage of the electronic device (paragraph [0041]). Regarding claim 2, Poon discloses the integrated circuit system of claim 1, wherein the voltage management circuit comprises at least one of a clamp high circuit and a clamp low circuit (paragraph [0041]) Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kumar et al. in view of Badaroglu et al. (US 2023/0115373, hereinafter “Badaroglu”). The only difference between claim 10 Kumar is that the electronic device comprises a single ended sense amplifier. However, Badaroglu discloses an SRAM device comprising a single-ended sense amplifier in each column of memory cells to sense data from the memory cell of the SRAM device. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use an SRAM device comprising a single-ended sense amplifier to sense data from the memory cell of the SRAM device. . Allowable Subject Matter Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 7, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “wherein the voltage management circuit comprises a first clamp high circuit electrically coupled to a clamp low circuit and the low clamp circuit being electrically coupled to a second clam high circuit.” in combination with the other limitations thereof as is recited in the claim. Claims 12-17 are allowed. Regarding claim 12, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “electrically coupling a port out of the second integrated circuit cell to a port in of a third integrated circuit cell, the first integrated circuit cell being a clamp high circuit, the second integrated circuit cell being a clamp low circuit, and the third integrated circuit cell being a clamp high circuit; and electrically coupling a port out of the third integrated circuit cell to an electronic device.” in combination with the other limitations thereof as is recited in the claim. Claims 13-17 depend on claim 12. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUAN HOANG whose telephone number is (571)272-1779. The examiner can normally be reached 7:30AM-4:00PM M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AMIR ZARABIAN can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HUAN HOANG/ Primary Examiner, Art Unit 2827
Read full office action

Prosecution Timeline

Dec 23, 2024
Application Filed
Jun 15, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12682937
PROCESSING IN MEMORY REGISTERS
1y 11m to grant Granted Jul 14, 2026
Patent 12681846
MEMORY AND OPERATING METHOD THEREOF
1y 10m to grant Granted Jul 14, 2026
Patent 12676177
DYNAMIC RANDOM ACCESS MEMORY (DRAM) WITH CONFIGURABLE WORDLINE AND BITLINE VOLTAGES
2y 7m to grant Granted Jul 07, 2026
Patent 12675258
CONTROL CIRCUIT, MEMORY SYSTEM, AND OPERATING METHOD
2y 1m to grant Granted Jul 07, 2026
Patent 12658238
ROW DECODERS HAVING TRANSISTORS PLACED IN A PLURALITY OF ROWS AND MEMORY DEVICES INCLUDING THE SAME
2y 6m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
93%
Grant Probability
99%
With Interview (+5.6%)
1y 8m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1224 resolved cases by this examiner. Grant probability derived from career allowance rate.

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