DETAILED ACTION
National Stage Application
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of pre-AIA 35 U.S.C. 112, second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 8-10 is/are rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claims 8-10 recite the limitation “the number”. There is insufficient antecedent basis for this limitation in the claims.
Claim(s) dependent on the claim(s) discussed above is/are also indefinite for the same reasons.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were effectively filed absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned at the time a later invention was effectively filed in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 8-11, and 13-17 is/are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Tumer et al. (US 2009/0290680).
In regard to claim 1, Tumer et al. disclose a radiation detector comprising: a conversion unit including a plurality of pixels generating carriers in response to incident radiation (e.g., “… converter layer in which high Z, high density photoconductive materials such as CdZnTe are used to achieve high x-ray quantum detection efficiency …” in paragraph 151), the plurality of pixels being arranged along a predetermined direction; and a plurality of pixel circuits each of which is provided corresponding to each of the plurality of pixels and has at least one detection system configured to read out the carriers from a corresponding pixel of the plurality of pixels (e.g., “… FIG. 7 shows the electronics used in one of the channels of a digital radiography system … digital radiography system (FIG. 7) may also be used as a multi energy imaging system … separation of the photons into separate energy bins can be done in different ways, such as using comparators … more and more bit counters will be required as the TDI section progresses down the TDI direction. Since the counter sizes are different along the TDI section the larger counters can share the area under the small counter pixels to reduce the size of the pixels …” in paragraphs 147 and 148), wherein the at least one detection system includes:
(a) a comparator comparing a first signal based on an amount of the carriers with a threshold value and outputting a second signal when the first signal exceeds the threshold value (e.g., “… input comes from a detector pixel into the input 701 of each channel … output of the amplifier and/or the gain stage goes to multiple comparators 705, 706 (two shown here). The comparators 705, 706 has thresholds 707, 708 controlled either by internal DACs or external circuitry … output of each comparator is counted by digital counters 709, 710 …” in paragraphs 147 and 186);
(b) a counter counting the number of second signals, each of which is the second signal (e.g., “… To reduce the delay to practically zero, the counts inside the counter can be shifted into a register, counters reset and the counting can start immediately …” in paragraph 186);
(c) a first register holding first data which is a count value of the counter (e.g., “… To reduce the delay to practically zero, the counts inside the counter can be shifted into a register, counters reset and the counting can start immediately …” in paragraph 186);
(d) a second register holding second data (e.g., “… Counter 1 803 in each cell is transferred in opposite direction 813 to the scan direction 814 into the Counter 1 806 of the adjacent cell 1 805 by the use of the transfer clock 815 … works without a need to have an adder circuit because when the counts accumulated is transferred from cell 1 802 Counter 1 803 to next cell's counter 1 it already contains the counts from the first cell. Therefore, when the counts are in the second cell's counter 1 806 this counter starts counting from the counts accumulated inside counter 803. Therefore, in this embodiment just transferring counts in sequence in the TDI direction 813 opposite to the scan direction 814 is sufficient to produce a natural DTDI process … To reduce the delay to practically zero, the counts inside the counter can be shifted into a register, counters reset and the counting can start immediately …” in paragraphs 171 and 186);
(e) an adder adding the first data and the second data to generate third data (e.g., “… Counter 1 803 in each cell is transferred in opposite direction 813 to the scan direction 814 into the Counter 1 806 of the adjacent cell 1 805 by the use of the transfer clock 815 … works without a need to have an adder circuit because when the counts accumulated is transferred from cell 1 802 Counter 1 803 to next cell's counter 1 it already contains the counts from the first cell. Therefore, when the counts are in the second cell's counter 1 806 this counter starts counting from the counts accumulated inside counter 803. Therefore, in this embodiment just transferring counts in sequence in the TDI direction 813 opposite to the scan direction 814 is sufficient to produce a natural DTDI process … To reduce the delay to practically zero, the counts inside the counter can be shifted into a register, counters reset and the counting can start immediately …” in paragraphs 171 and 186); and
(f) a third register holding the third data (e.g., “… Counter 1 803 in each cell is transferred in opposite direction 813 to the scan direction 814 into the Counter 1 806 of the adjacent cell 1 805 by the use of the transfer clock 815 … works without a need to have an adder circuit because when the counts accumulated is transferred from cell 1 802 Counter 1 803 to next cell's counter 1 it already contains the counts from the first cell. Therefore, when the counts are in the second cell's counter 1 806 this counter starts counting from the counts accumulated inside counter 803. Therefore, in this embodiment just transferring counts in sequence in the TDI direction 813 opposite to the scan direction 814 is sufficient to produce a natural DTDI process … To reduce the delay to practically zero, the counts inside the counter can be shifted into a register, counters reset and the counting can start immediately …” in paragraphs 171 and 186), and
the second data is the third data transferred from the third register of a pixel circuit provided corresponding to a pixel adjacent to a corresponding pixel of the plurality of pixels in each of the plurality of pixel circuits (e.g., “… Counter 1 803 in each cell is transferred in opposite direction 813 to the scan direction 814 into the Counter 1 806 of the adjacent cell 1 805 by the use of the transfer clock 815 … works without a need to have an adder circuit because when the counts accumulated is transferred from cell 1 802 Counter 1 803 to next cell's counter 1 it already contains the counts from the first cell. Therefore, when the counts are in the second cell's counter 1 806 this counter starts counting from the counts accumulated inside counter 803. Therefore, in this embodiment just transferring counts in sequence in the TDI direction 813 opposite to the scan direction 814 is sufficient to produce a natural DTDI process … To reduce the delay to practically zero, the counts inside the counter can be shifted into a register, counters reset and the counting can start immediately …” in paragraphs 171 and 186).
Alternatively it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that “counters reset and the counting can start immediately” can be achieved by providing “an adder circuit” for each of the “counters” wherein “counts inside the counter can be shifted into” one of the adder circuit’s input registers and another of the adder circuit’s input registers is for receiving a transfer from an adjacent pixel’s adder circuit’s output register using one of the “transfer clocks”.
In regard to claim 2 which is dependent on claim 1, Tumer et al. also disclose that the adder includes at least one of the first register, the second register, and the third register (e.g., “… Counter 1 803 in each cell is transferred in opposite direction 813 to the scan direction 814 into the Counter 1 806 of the adjacent cell 1 805 by the use of the transfer clock 815 … works without a need to have an adder circuit because when the counts accumulated is transferred from cell 1 802 Counter 1 803 to next cell's counter 1 it already contains the counts from the first cell. Therefore, when the counts are in the second cell's counter 1 806 this counter starts counting from the counts accumulated inside counter 803. Therefore, in this embodiment just transferring counts in sequence in the TDI direction 813 opposite to the scan direction 814 is sufficient to produce a natural DTDI process … To reduce the delay to practically zero, the counts inside the counter can be shifted into a register, counters reset and the counting can start immediately …” in paragraphs 171 and 186), and the at least one detection system has other registers excluding the at least one of the first register, the second register, and the third register outside the adder (e.g., “… FIG. 8 is a block diagram of a 160 cell DTDI circuit with two counters in each cell. There is no limitation on the number of cells and/or comparators and/or counters per cell. Therefore, same design can be extended to include more than 2 counters per pixel or channel … Counter 2 804 is also transferred similarly into the Counter 2 807 of the neighboring cell by the use of the transfer clock 815. The two counters may have separate transfer clocks … works without a need to have an adder circuit because when the counts accumulated is transferred from cell 1 802 Counter 1 803 to next cell's counter 1 it already contains the counts from the first cell. Therefore, when the counts are in the second cell's counter 1 806 this counter starts counting from the counts accumulated inside counter 803. Therefore, in this embodiment just transferring counts in sequence in the TDI direction 813 opposite to the scan direction 814 is sufficient to produce a natural DTDI process … To reduce the delay to practically zero, the counts inside the counter can be shifted into a register, counters reset and the counting can start immediately …” in paragraphs 171 and 186). Alternatively it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that “counters reset and the counting can start immediately” can be achieved by providing “an adder circuit” for each of the “counters” wherein “counts inside the counter can be shifted into” one of the adder circuit’s input registers and another of the adder circuit’s input registers is for receiving a transfer from an adjacent pixel’s adder circuit’s output register using one of the “transfer clocks”.
In regard to claims 3 and 4 which are dependent on claim 1, Tumer et al. also disclose that, in each of the plurality of pixel circuits, an area of a first region occupied by an analog circuit including the comparator is larger than an area of a second region occupied by a digital circuit including the counter, the first register, the second register, the adder, and the third register, wherein the area of the first region is equal to or larger than half of an entire area of each of the plurality of pixel circuits (e.g., “… signal is then amplified by an amplifier 702, which is a charge sensitive type, it has feedback element 703, a gain stage 704 may be used, and the output of the amplifier and/or the gain stage goes to multiple comparators 705, 706 (two shown here). The comparators 705, 706 has thresholds 707, 708 controlled either by internal DACs or external circuitry, the outputs of the comparators 705, 706 goes to counters 709, 710, respectively. The counters are read out in sequence from previous stage 711 to next stage 712, or in parallel. The counters in different channels may also be linked in the same way for readout … counting of the pulses from the detector pixels can be also done in different ways such as analog counters, digital counters, mixture of analog and digital counters, TDI for each energy bin, etc. If small sections of TDI are used such as N sections then the count rate at the beginning pixel of a TDI channel with total TDI counts of C will have C*(1/N) counts. The next channel will have C*(2/N), so on. Therefore, the digital or analog counters at the beginning of each TDI section will use a small number of bits. And more and more bit counters will be required as the TDI section progresses down the TDI direction. Since the counter sizes are different along the TDI section the larger counters can share the area under the small counter pixels to reduce the size of the pixels …” in paragraphs 147 and 148). Alternatively it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that “reduce the size of the pixels” can be achieved by providing “small counter pixels” with limited digital circuitry area (e.g., less than halve of “size of the pixels”).
In regard to claim 5 which is dependent on claim 1, Tumer et al. also disclose that each of the plurality of pixel circuits has a plurality of detection systems as the at least one detection system, and threshold values in the plurality of detection systems, each of which is the threshold value of the comparator, are different for each detection system (e.g., “… comparator 705, 706 type electronics readout system can be used as described above to divide the incoming x-ray or gamma ray photons into different energy bins. The is number of photons in each energy bin is then counted 709, 710 separately …” in paragraph 148).
In regard to claim 6 which is dependent on claim 5, Tumer et al. also disclose that adders in the plurality of detection systems, each of which is the adder, are individually provided for each detection system (e.g., “… FIG. 8 is a block diagram of a 160 cell DTDI circuit with two counters in each cell. There is no limitation on the number of cells and/or comparators and/or counters per cell. Therefore, same design can be extended to include more than 2 counters per pixel or channel … Counter 2 804 is also transferred similarly into the Counter 2 807 of the neighboring cell by the use of the transfer clock 815. The two counters may have separate transfer clocks … works without a need to have an adder circuit because when the counts accumulated is transferred from cell 1 802 Counter 1 803 to next cell's counter 1 it already contains the counts from the first cell. Therefore, when the counts are in the second cell's counter 1 806 this counter starts counting from the counts accumulated inside counter 803. Therefore, in this embodiment just transferring counts in sequence in the TDI direction 813 opposite to the scan direction 814 is sufficient to produce a natural DTDI process … To reduce the delay to practically zero, the counts inside the counter can be shifted into a register, counters reset and the counting can start immediately …” in paragraphs 171 and 186). Alternatively it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that “counters reset and the counting can start immediately” can be achieved by providing “an adder circuit” for each of the “counters” wherein “counts inside the counter can be shifted into” one of the adder circuit’s input registers and another of the adder circuit’s input registers is for receiving a transfer from an adjacent pixel’s adder circuit’s output register using one of the “transfer clocks”.
In regard to claim 8 which is dependent on claim 1 in so far as understood, Tumer et al. also disclose that the number of bits of the second register is equal to or larger than a sum of the number of bits of the first register and the number of bits which is a binary representation of the number of the plurality of pixel circuits, and the number of bits of the adder is equal to the number of bits of the second register (e.g., “… counters at the beginning of each TDI section will use a small number of bits. And more and more bit counters will be required as the TDI section progresses down the TDI direction … counter bit circuits are arrayed in a ripple carry adder … an adder circuit … If the total counts at the end of DTDI is over 16 bits then we have several options: 1. Increase the counters to 17 bit or higher, 2. Drop least significant bits, and/or 3. Use small number of bit counters at the beginning cells and larger counters in the pixels at the end of the DTDI chain … To reduce the delay to practically zero, the counts inside the counter can be shifted into a register, counters reset and the counting can start immediately …” in paragraphs148, 169, 171 and 174). Alternatively it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to design bit numbers of “adder circuit” for “larger counters in the pixels at the end of the DTDI chain” in order to achieve “counters reset and the counting can start immediately” without dropping bits.
In regard to claim 9 which is dependent on claim 1 in so far as understood, Tumer et al. also disclose that the number of bits of the second register is equal to or larger than a sum of the number of bits of the first register and the number of bits which is a binary representation of the number of the plurality of pixel circuits, the number of bits of the adder is smaller than the number of bits of the second register, and the adder repeatedly performs an operation of adding some bits of the first data in the first register and some bits of the second data in the second register corresponding to the some bits of the first data and outputting a result of the adding until all of the bits of the first data are added (e.g., “… counters at the beginning of each TDI section will use a small number of bits. And more and more bit counters will be required as the TDI section progresses down the TDI direction … counter bit circuits are arrayed in a ripple carry adder … an adder circuit … If the total counts at the end of DTDI is over 16 bits then we have several options: 1. Increase the counters to 17 bit or higher, 2. Drop least significant bits, and/or 3. Use small number of bit counters at the beginning cells and larger counters in the pixels at the end of the DTDI chain … To reduce the delay to practically zero, the counts inside the counter can be shifted into a register, counters reset and the counting can start immediately …” in paragraphs148, 169, 171 and 174). Alternatively it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to design bit numbers of “adder circuit” for “larger counters in the pixels at the end of the DTDI chain” in order to achieve “counters reset and the counting can start immediately” without dropping bits.
In regard to claim 10 which is dependent on claim 9 in so far as understood, Tumer et al. also disclose that the number of bits of the adder is one, and the adder has a fourth register for holding a carry signal (e.g., “… counter bit circuits are arrayed in a ripple carry adder …” in paragraph 169).
In regard to claim 11 which is dependent on claim 1, Tumer et al. also disclose that each of the plurality of pixel circuits further includes a charge sharing countermeasure circuit that, when the carriers generated by an incidence of the radiation are dispersively read out to two or more of pixel circuits of the plurality of pixel circuits, determines a pixel of the plurality of pixels corresponding to a position where the radiation is incident and corrects and evaluates the amount of carriers in the pixel, or ignores the incidence of the radiation (e.g., “… In a small pixel 2-D detector it is quite likely that the charge is shared between adjacent pixels. Therefore, one or two or three neighboring pixels may produce a trigger but the other pixels surrounding them may also have some charge. Therefore, to get the maximum energy resolution it is good to read out the charge collected by the neighboring pixels. In this mode, the chip produces a hit register, which shows which pixels produced a trigger. The external circuitry downloads the hit register and then it automatically reads the pixels, which produced a trigger and also the neighboring pixels around them. This is only necessary if probability for charge sharing is significant, which is true for small pixel size and thick detectors …” in paragraph 110). Alternatively it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to evaluate if “charge is shared between adjacent pixels” in order “to get the maximum energy resolution” by correcting using “read out the charge collected by the neighboring pixels”.
In regard to claim 13 which is dependent on claim 1, Tumer et al. also disclose that each of the plurality of pixel circuits further includes a shaper circuit provided in a stage preceding the comparator, and the shaper circuit reduces a time constant of the first signal (e.g., “… signal is then amplified by an amplifier 702, which is a charge sensitive type, it has feedback element 703, a gain stage 704 may be used, and the output of the amplifier and/or the gain stage goes to multiple comparators 705, 706 (two shown here) … optimized to match the input capacitance of the detector pixel … external current input is used to control the ratio of feedback current and thus the input amplifier time constant …” in paragraphs 147, 162, and 163).
In regard to claim 14 which is dependent on claim 1, Tumer et al. also disclose that the plurality of pixel circuits have a first pixel circuit region and a second pixel circuit region, and the first data is stored in the first register at different timings in the first pixel circuit region and the second pixel circuit region (e.g., “… counters may have separate transfer clocks … To reduce the delay to practically zero, the counts inside the counter can be shifted into a register, counters reset and the counting can start immediately …” in paragraphs 171 and 186). Alternatively it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that “counters reset and the counting can start immediately” can be achieved by providing “an adder circuit” for each of the “counters” wherein “counts inside the counter can be shifted into” one of the adder circuit’s input registers and another of the adder circuit’s input registers is for receiving a transfer from an adjacent pixel’s adder circuit’s output register using one of the “transfer clocks”.
In regard to claim 15 which is dependent on claim 14, Tumer et al. also disclose a power supply supplying a power supply voltage to each of the plurality of pixel circuits through a power transmission line; and a control unit configured to transmit a hold signal to each of the plurality of pixel circuits through a signal line, wherein the second pixel circuit region is arranged with the first pixel circuit region along a predetermined direction, and a direction in which the power transmission line is branched intersects a direction in which the signal line is branched and the predetermined direction (e.g., “… pixel capacitance. The ASIC's input MOSFET transistor for the charge sensitive amplifier has been optimized through SPICE simulations to achieve minimum noise. In addition, the transistor gate size is designed to match the detector input capacitance … input can be also turned on and off so that the chip does not process any input signals until the inputs are turned on … counters may have separate transfer clocks … To reduce the delay to practically zero, the counts inside the counter can be shifted into a register, counters reset and the counting can start immediately … ASIC and the readout electronics can be designed for low power consumption so that compact, portable and battery operated radiation detection equipment can be developed …” in paragraphs 87, 147, 171, 186, and 190). Alternatively it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to optimize routing (e.g., a direction in which the power transmission line is branched intersects a direction in which the signal line is branched and the predetermined direction) “through SPICE simulations” in order “to achieve minimum noise”.
In regard to claim 16, Tumer et al. disclose an integrated circuit (e.g., “… chip …” in paragraph 147) comprising: a plurality of pixel circuits each of which is provided corresponding to each of a plurality of pixels generating carriers in response to incident radiation, the plurality of pixels being arranged along a predetermined direction, each of the plurality of pixel circuits having at least one detection system configured to read out the carriers from a corresponding pixel of the plurality of pixels (e.g., “… FIG. 7 shows the electronics used in one of the channels of a digital radiography system … digital radiography system (FIG. 7) may also be used as a multi energy imaging system … separation of the photons into separate energy bins can be done in different ways, such as using comparators … more and more bit counters will be required as the TDI section progresses down the TDI direction. Since the counter sizes are different along the TDI section the larger counters can share the area under the small counter pixels to reduce the size of the pixels …” in paragraphs 147 and 148), wherein the at least one detection system includes:
(a) a comparator comparing a first signal based on an amount of the carriers with a threshold value and outputting a second signal when the first signal exceeds the threshold value (e.g., “… input comes from a detector pixel into the input 701 of each channel … output of the amplifier and/or the gain stage goes to multiple comparators 705, 706 (two shown here). The comparators 705, 706 has thresholds 707, 708 controlled either by internal DACs or external circuitry … output of each comparator is counted by digital counters 709, 710 …” in paragraphs 147 and 186);
(b) a counter counting the number of second signals, each of which is the second signal (e.g., “… To reduce the delay to practically zero, the counts inside the counter can be shifted into a register, counters reset and the counting can start immediately …” in paragraph 186);
(c) a first register holding first data which is a count value of the counter (e.g., “… To reduce the delay to practically zero, the counts inside the counter can be shifted into a register, counters reset and the counting can start immediately …” in paragraph 186);
(d) a second register holding second data (e.g., “… Counter 1 803 in each cell is transferred in opposite direction 813 to the scan direction 814 into the Counter 1 806 of the adjacent cell 1 805 by the use of the transfer clock 815 … works without a need to have an adder circuit because when the counts accumulated is transferred from cell 1 802 Counter 1 803 to next cell's counter 1 it already contains the counts from the first cell. Therefore, when the counts are in the second cell's counter 1 806 this counter starts counting from the counts accumulated inside counter 803. Therefore, in this embodiment just transferring counts in sequence in the TDI direction 813 opposite to the scan direction 814 is sufficient to produce a natural DTDI process … To reduce the delay to practically zero, the counts inside the counter can be shifted into a register, counters reset and the counting can start immediately …” in paragraphs 171 and 186);
(e) an adder adding the first data and the second data to generate third data (e.g., “… Counter 1 803 in each cell is transferred in opposite direction 813 to the scan direction 814 into the Counter 1 806 of the adjacent cell 1 805 by the use of the transfer clock 815 … works without a need to have an adder circuit because when the counts accumulated is transferred from cell 1 802 Counter 1 803 to next cell's counter 1 it already contains the counts from the first cell. Therefore, when the counts are in the second cell's counter 1 806 this counter starts counting from the counts accumulated inside counter 803. Therefore, in this embodiment just transferring counts in sequence in the TDI direction 813 opposite to the scan direction 814 is sufficient to produce a natural DTDI process … To reduce the delay to practically zero, the counts inside the counter can be shifted into a register, counters reset and the counting can start immediately …” in paragraphs 171 and 186); and
(f) a third register holding the third data (e.g., “… Counter 1 803 in each cell is transferred in opposite direction 813 to the scan direction 814 into the Counter 1 806 of the adjacent cell 1 805 by the use of the transfer clock 815 … works without a need to have an adder circuit because when the counts accumulated is transferred from cell 1 802 Counter 1 803 to next cell's counter 1 it already contains the counts from the first cell. Therefore, when the counts are in the second cell's counter 1 806 this counter starts counting from the counts accumulated inside counter 803. Therefore, in this embodiment just transferring counts in sequence in the TDI direction 813 opposite to the scan direction 814 is sufficient to produce a natural DTDI process … To reduce the delay to practically zero, the counts inside the counter can be shifted into a register, counters reset and the counting can start immediately …” in paragraphs 171 and 186), and
the second data is the third data transferred from the third register of a pixel circuit provided corresponding to a pixel adjacent to a corresponding pixel of the plurality of pixels in each of the plurality of pixel circuits (e.g., “… Counter 1 803 in each cell is transferred in opposite direction 813 to the scan direction 814 into the Counter 1 806 of the adjacent cell 1 805 by the use of the transfer clock 815 … works without a need to have an adder circuit because when the counts accumulated is transferred from cell 1 802 Counter 1 803 to next cell's counter 1 it already contains the counts from the first cell. Therefore, when the counts are in the second cell's counter 1 806 this counter starts counting from the counts accumulated inside counter 803. Therefore, in this embodiment just transferring counts in sequence in the TDI direction 813 opposite to the scan direction 814 is sufficient to produce a natural DTDI process … To reduce the delay to practically zero, the counts inside the counter can be shifted into a register, counters reset and the counting can start immediately …” in paragraphs 171 and 186).
Alternatively it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that “counters reset and the counting can start immediately” can be achieved by providing “an adder circuit” for each of the “counters” wherein “counts inside the counter can be shifted into” one of the adder circuit’s input registers and another of the adder circuit’s input registers is for receiving a transfer from an adjacent pixel’s adder circuit’s output register using one of the “transfer clocks”.
In regard to claim 17, Tumer et al. disclose a radiation detection method comprising:
(a) generating carriers in response to incident radiation in a plurality of pixels arranged along a predetermined direction (e.g., “… FIG. 7 shows the electronics used in one of the channels of a digital radiography system … digital radiography system (FIG. 7) may also be used as a multi energy imaging system … separation of the photons into separate energy bins can be done in different ways, such as using comparators … more and more bit counters will be required as the TDI section progresses down the TDI direction. Since the counter sizes are different along the TDI section the larger counters can share the area under the small counter pixels to reduce the size of the pixels …” in paragraphs 147 and 148);
(b) reading out the carriers from a corresponding pixel of the plurality of pixels in a plurality of pixel circuits provided corresponding to the plurality of pixels, respectively (e.g., “… input comes from a detector pixel into the input 701 of each channel …” in paragraph 147);
(c) comparing a first signal based on an amount of the carriers with a threshold value and outputting a second signal when the first signal exceeds the threshold value (e.g., “… output of the amplifier and/or the gain stage goes to multiple comparators 705, 706 (two shown here). The comparators 705, 706 has thresholds 707, 708 controlled either by internal DACs or external circuitry … output of each comparator is counted by digital counters 709, 710 …” in paragraphs 147 and 186);
(d) counting the number of second signals, each of which is the second signal (e.g., “… To reduce the delay to practically zero, the counts inside the counter can be shifted into a register, counters reset and the counting can start immediately …” in paragraph 186);
(e) holding first data, which is a count value in the counting, in a first register (e.g., “… To reduce the delay to practically zero, the counts inside the counter can be shifted into a register, counters reset and the counting can start immediately …” in paragraph 186);
(f) holding second data in a second register (e.g., “… Counter 1 803 in each cell is transferred in opposite direction 813 to the scan direction 814 into the Counter 1 806 of the adjacent cell 1 805 by the use of the transfer clock 815 … works without a need to have an adder circuit because when the counts accumulated is transferred from cell 1 802 Counter 1 803 to next cell's counter 1 it already contains the counts from the first cell. Therefore, when the counts are in the second cell's counter 1 806 this counter starts counting from the counts accumulated inside counter 803. Therefore, in this embodiment just transferring counts in sequence in the TDI direction 813 opposite to the scan direction 814 is sufficient to produce a natural DTDI process … To reduce the delay to practically zero, the counts inside the counter can be shifted into a register, counters reset and the counting can start immediately …” in paragraphs 171 and 186);
(g) adding the first data and the second data to generate third data (e.g., “… Counter 1 803 in each cell is transferred in opposite direction 813 to the scan direction 814 into the Counter 1 806 of the adjacent cell 1 805 by the use of the transfer clock 815 … works without a need to have an adder circuit because when the counts accumulated is transferred from cell 1 802 Counter 1 803 to next cell's counter 1 it already contains the counts from the first cell. Therefore, when the counts are in the second cell's counter 1 806 this counter starts counting from the counts accumulated inside counter 803. Therefore, in this embodiment just transferring counts in sequence in the TDI direction 813 opposite to the scan direction 814 is sufficient to produce a natural DTDI process … To reduce the delay to practically zero, the counts inside the counter can be shifted into a register, counters reset and the counting can start immediately …” in paragraphs 171 and 186); and
(h) holding the third data in a third register (e.g., “… Counter 1 803 in each cell is transferred in opposite direction 813 to the scan direction 814 into the Counter 1 806 of the adjacent cell 1 805 by the use of the transfer clock 815 … works without a need to have an adder circuit because when the counts accumulated is transferred from cell 1 802 Counter 1 803 to next cell's counter 1 it already contains the counts from the first cell. Therefore, when the counts are in the second cell's counter 1 806 this counter starts counting from the counts accumulated inside counter 803. Therefore, in this embodiment just transferring counts in sequence in the TDI direction 813 opposite to the scan direction 814 is sufficient to produce a natural DTDI process … To reduce the delay to practically zero, the counts inside the counter can be shifted into a register, counters reset and the counting can start immediately …” in paragraphs 171 and 186),
wherein the second data is the third data transferred from the third register of a pixel circuit provided corresponding to a pixel adjacent to a corresponding pixel of the plurality of pixels in each of the plurality of pixel circuits (e.g., “… Counter 1 803 in each cell is transferred in opposite direction 813 to the scan direction 814 into the Counter 1 806 of the adjacent cell 1 805 by the use of the transfer clock 815 … works without a need to have an adder circuit because when the counts accumulated is transferred from cell 1 802 Counter 1 803 to next cell's counter 1 it already contains the counts from the first cell. Therefore, when the counts are in the second cell's counter 1 806 this counter starts counting from the counts accumulated inside counter 803. Therefore, in this embodiment just transferring counts in sequence in the TDI direction 813 opposite to the scan direction 814 is sufficient to produce a natural DTDI process … To reduce the delay to practically zero, the counts inside the counter can be shifted into a register, counters reset and the counting can start immediately …” in paragraphs 171 and 186).
Alternatively it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that “counters reset and the counting can start immediately” can be achieved by providing “an adder circuit” for each of the “counters” wherein “counts inside the counter can be shifted into” one of the adder circuit’s input registers and another of the adder circuit’s input registers is for receiving a transfer from an adjacent pixel’s adder circuit’s output register using one of the “transfer clocks”.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tumer et al. (US 2009/0290680) in view of Kelly et al. (US 2010/0226495).
In regard to claim 7 which is dependent on claim 5, while Tumer et al. also disclose (paragraph 171) “… transferring counts in sequence in the TDI direction …”, the detector of Tumer et al. lacks an explicit description of details of the “… counts …” such as the adder in each of the plurality of detection systems is common to the plurality of detection systems. However, “… counts* …” details are known to one of ordinary skill in the art (e.g., see “… readout integrated circuit in accordance with the principles of the present invention allows a single pixel (unit cell) counter to be shared among 4 or more virtual pixels; the available dynamic range (i.e., bits) within a single ROIC unit cell can therefore be optimized between intensity dynamic range and spatial resolution …” in paragraph 128 of Kelly et al.). It should be noted that “when a patent claims a structure already known in the prior art that is altered by the mere substitution of one element for another known in the field, the combination must do more than yield a predictable results”. KSR International Co. v. Teleflex Inc., 550 U.S. 398 at 416, 82 USPQ2d 1385 (2007) at 1395 (citing United States v. Adams, 383 U.S. 39, 40 [148 USPQ 479] (1966)). See MPEP § 2143. In this case, one of ordinary skill in the art could have substituted a known conventional counting (e.g., comprising details such as “shared among 4 or more virtual pixels”, in order to be “optimized between intensity dynamic range and spatial resolution”) for the counting of Tumer et al. and the results of the substitution would have been predictable. Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a known conventional counting (e.g., comprising details such as the adder in each of the plurality of detection systems is common to the plurality of detection systems) as the counting of Tumer et al.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tumer et al. (US 2009/0290680) in view of De Godzinsky (US 2009/0242779).
In regard to claim 12 which is dependent on claim 1, while Tumer et al. also disclose (paragraph 171) “… transferring counts in sequence in the TDI direction …”, the detector of Tumer et al. lacks an explicit description of details of the “… TDI direction …” such as the plurality of pixel circuits further include a switching unit for switching between an operation of transferring the third data along the predetermined direction and an operation of transferring the third data along a direction opposite to the predetermined direction. However, “… TDI direction …” details are known to one of ordinary skill in the art (e.g., see “… it is possible to use an arrangement where the counters 27, besides being loaded in one direction, can also be loaded in both directions, allowing the sensor to be used for TDI imaging in opposite directions …” in paragraph 15 of De Godzinsky). It should be noted that “when a patent claims a structure already known in the prior art that is altered by the mere substitution of one element for another known in the field, the combination must do more than yield a predictable results”. KSR International Co. v. Teleflex Inc., 550 U.S. 398 at 416, 82 USPQ2d 1385 (2007) at 1395 (citing United States v. Adams, 383 U.S. 39, 40 [148 USPQ 479] (1966)). See MPEP § 2143. In this case, one of ordinary skill in the art could have substituted a known conventional TDI (e.g., comprising details such as “counters 27, besides being loaded in one direction, can also be loaded in both directions”, in order for “TDI imaging in opposite directions”) for the TDI of Tumer et al. and the results of the substitution would have been predictable. Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a known conventional TDI (e.g., comprising details such as the plurality of pixel circuits further include a switching unit for switching between an operation of transferring the third data along the predetermined direction and an operation of transferring the third data along a direction opposite to the predetermined direction) as the TDI of Tumer et al.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 5,943,388 teaches a readout circuit.
US 2004/0212708 teaches TDI.
US 2014/0131588 teaches a readout circuit.
US 2022/0221596 teaches a readout circuit.
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/SL/
Examiner, Art Unit 2884
/UZMA ALAM/Supervisory Patent Examiner, Art Unit 2884
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