Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed December 31, 2024.
Status of claims to be treated in this office action:
a. Independent: 1, 13, 18
b. Pending: 1-20
Claims 1-20 have been amended through preliminary amendments.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The following phrase from the second limitation of claim 13 is indefinite: “to bias the digit line to an inhibit voltage applied to another end portion of the pillar”. Does enabling of the TFT cause the digit line to be biased and does that enabling also inhibit the other end of the pillar? Also, it is unclear what component is inhibited and how.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US Pub. 20020028541 A1; “Lee”) in view of Chen et al. (US Pub. 20130336037 A1; “Chen”), Kuwabara et al. (US Pub. 20090279012 A1; “Kuwabara”), and Murooka (US Pub. 20190067376 A1).
Regarding independent claim 1, Lee discloses a memory device (Fig. 52: three dimensional memory array 4400; [0256]; [0259]: array of nonvolatile memory devices 4400) comprising:
a plurality of pillars (plurality of bit line columns 4425; [0257]) extending through a plurality of levels of a memory array (device level 4445; [0259]);
one or more memory cells of the memory array ([0260]: Each cell in one level 4445 of the memory array) coupled with a respective pillar and a respective word line at each level of the plurality of levels ([0257]: The source and drain regions are formed in the bit lines where the word lines intersect (i.e., overlie) the bit lines and the doped regions are located adjacent to the EEPROM channel regions; );
a digit line (4425);
a plurality of thin film transistors ([0257]: a plurality of TFT EEPROMs), wherein the plurality of pillars, the one or more memory cells and the plurality of thin film transistors are positioned in a first area of the memory array ([0257]: The memory array also contains a plurality of bit line columns 4425, each bit line contacting the source or the drain regions 4417 of a plurality of TFT EEPROMs. The columns of the bit lines 4425 extend substantially perpendicular to the source-channel-drain direction of the TFT EEPROMs. Examiner asserts that the area described is analogous to a first area), and wherein the digit line extends in the first area and at least partially in a second area outside the first area ([0257]: The bit lines in each device level are shaped as rails which extend under the intergate insulating layer); and
a driver for the digit line,
positioned in the second area ([0384]: A peripheral or driver circuit (not shown) is arranged in the substrate, preferably below the array and at least in partial vertical alignment with the array, or alternatively, within or above the array and at least in partial vertical alignment with the array).
Lee does not disclose:
each TFT being configured to selectively couple the digit line with a respective pillar,
a driver for the digit line, the driver comprising a first TFT, a second TFT and a pillar, wherein the first TFT, the second TFT and the pillar are positioned in the second area.
However, Chen teaches:
each TFT being configured to selectively couple the digit line with a respective pillar (claim 8: a 2D array of isolated TFT channels in the x-y plane of the slab, each TFT channel being in-line with and having a first end connected to one end of one of the bit line pillars along the z-direction),
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Chen to
Lee wherein each TFT being configured to selectively couple the digit line with a respective pillar in order to implement a memory device with TFTs to improve switching and driving capacity (Chen, [0013]).
Also, through Kuwabara:
the driver (Fig. 15: scan line side driver circuit; [0231]) comprising a first TFT, a second TFT (the scan line side driver circuit of Fig. 15 comprises pulse output circuit 500; [0233]: FIG. 16 shows a specific structure of the pulse output circuit 500, and the circuit is configured by n-channel type TFTs 601 to 612)
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Kuwabara to modified Lee wherein the driver comprises a first TFT and a second TFT in order to provide a semiconductor device which includes thin film transistors and solves a signal delay problem (Kuwabara, [0001] & [0015]).
Also, through Murooka:
a driver comprising a pillar ([0064]: The GBL decoder 23 includes a global bit line selection unit and a global bit line driver; [0053]: pillar-shaped bit lines BL. Examiner asserts that the global bit line driver comprises a pillar because the driver is coupled to the bit lines, which are pillar-shaped)
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Murooka to modified Lee wherein the driver comprises a pillar in order to provide a semiconductor device using high-integration ReRAM with a thin film variable resistance material (Murooka, [0003] & [0053]).
Regarding claim 2, Lee, Chen, Kuwabara, and Murooka together disclose all the limitations of claim 1, and further through Lee:
wherein the digit line is coupled to the first TFT and to the second TFT ([0026]: each bit line contacting the source or the drain regions of the TFT EEPROMs).
3.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US Pub. 20020028541 A1) in view of Chen (US Pub. 20130336037 A1), Kuwabara (US Pub. 20090279012 A1), Murooka (US Pub. 20190067376 A1), and Castro et al. (US Pub. 20200194431 A1; “Castro”).
Independent claim 13 contains a first limitation that is substantially the same in claimed subject matter to the first four limitations of independent claim 1, and that limitation is therefore rejected for the same reasons using Lee, Chen, Kuwabara, and Murooka. The limitations “coupled between the digit line and an end portion of a pillar” and “wherein the first TFT, the second TFT and the pillar are positioned in the second area” are also taught by a combination of Lee, Chen, Kuwabara, and Murooka, per claim 1 rejection above.
Neither Lee, Chen, Kuwabara, nor Murooka discloses:
selectively enabling a first TFT, to bias the digit line to an inhibit voltage applied to another end portion of the pillar, and a second TFT, coupled between the digit line and a conductive line, to bias the digit line to an access voltage applied to the conductive line, wherein the first TFT, the second TFT and the pillar are positioned in the second area.
However, Castro teaches:
selectively enabling a first TFT ([0024]: TFTs may be coupled with the access lines (e.g., word lines, bit lines, first array electrodes, second array electrodes) and thus support selecting (and accessing) multiple decks of memory cells disposed in the cross-point architecture), to bias the digit line to an inhibit voltage applied to another end portion of the pillar ([0217]: TFTs coupled with an inhibit node of bit line inhibit driver 737-b (e.g., TFTs coupled with common node 797-f) may be activated or deactivated (e.g., six TFTs are activated and two TFTs are deactivated as depicted in circuit diagram 738-b) such that the activated TFTs may couple unselected bit lines (e.g., BL1, BL2, BL4) with the inhibit node of bit line inhibit driver 737-b. See Fig. 7D), and a second TFT, coupled between the digit line and a conductive line, to bias the digit line to an access voltage applied to the conductive line ([0160]: FIG. 5N also illustrates that more than one TFTs (e.g., wrap-around TFTs) may be concatenated to provide a greater amount of current than a current that a single TFT may provide…FIG. 5N depicts five (5) single TFTs concatenated into one TFT (e.g., as indicated by five conductive plugs arranged in a single column that are connected to a single electrode tab 555-a) that may supply five times more current than a single TFT),
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Castro to modified Lee wherein the method comprises selectively enabling a first TFT, to bias the digit line to an inhibit voltage applied to another end portion of the pillar, and a second TFT, coupled between the digit line and a conductive line, to bias the digit line to an access voltage applied to the conductive line, wherein the first TFT, the second TFT and the pillar are positioned in the second area in order to implement multiple memory decks while maintaining a small footprint (Castro, [0020]).
Allowable Subject Matter
Claims 18-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Independent claim 18 includes allowable subject matter since the prior art
made of record and considered pertinent to the applicant’s disclosure, taken individually
or in combination, does not teach or suggest the claimed invention having:
“a first TFT coupled between a respective digit line and a respective dummy pillar having an end coupled to a source of a inhibit voltage (VSS)”
“a second TFT coupled between the respective digit line and a respective conductive line f35-1j coupled to an access voltage (VPP).”
The Examiner was not able to find additional references to logically combine with
Lee, Chen, Kuwabara, Murooka, and Castro in order to reject the other above features of claim 18.
Claims 3-12, and 14-17 are objected to as being dependent upon a rejected
base claim, but would be allowable if rewritten in independent form including all of the
limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIZABETH ROSE AGGER whose telephone number is (571)270-0250. The examiner can normally be reached Mon-Fri, 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rich Elms can be reached at 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/E.R.A./Examiner, Art Unit 2824
/HAN YANG/Primary Examiner, Art Unit 2824
7/11/2026
Prosecution Insights