Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed January 7, 2025.
Status of claims to be treated in this office action:
a. Independent: 1, 19, 20
b. Pending: 1-20
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 19, and 20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Baek et al. (US Pub. 20110194338 A1; “Baek”).
Regarding independent claim 1, Baek discloses a storage device (Figs. 1B & 1C: integrated circuit memory device; [0038]) comprising:
a magnetoresistive storage element ([0040]: Each magnetic memory element 111 may be programmable to at least two different magnetoresistive states determined by a magnetic polarization of the free magnetic layer 111a relative to the fixed magnetic layer 111c of the magnetic memory element 111) that can be changed to at least four identifiable resistance states ([0044]: FIG. 2…lines 1, 2, 3, and 4 illustrate resistance characteristics of a memory cell Mc at each of four different programmed resistance states); and
a write unit (Fig. 1A: controller 119; [0038]: the memory cells Mc may be separately addressed by controller 119 during read and write operations. Examiner asserts that the controller 119 may function as a write unit) that changes the magnetoresistive storage element into the at least four identifiable resistance states ([0044]) by changing a magnetization direction of the magnetoresistive storage element or causing a blow current to flow through the magnetoresistive storage element ([0042]: The controller 119 may be further configured to apply one of a plurality of different electrical switching currents I_Sw through the memory cell Mc including the resistive memory element 115 to program one of the at least two different resistance states of the resistive memory element 115. Examiner notes that a switching current is equivalent to a blow current).
Independent claims 19 and 20 contain substantially the same subject matter as the limitations of independent claim 1, except for being written to an apparatus and a method, respectively, and are thus rejected for the same reasons using Baek.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Baek (US Pub. 20110194338 A1) as applied to claim 1 above, and further in view of Aggarwal et al. (US Pub. 20190221609 A1; “Aggarwal”).
Regarding claim 2, Baek discloses the limitations of claim 1, and further through Baek:
wherein the magnetoresistive storage element ([0040]) includes a magnetization fixed layer, a storage layer, an insulating layer provided between the magnetization fixed layer and the storage layer ([0039]: Each magnetic memory element 111 may include a tunnel insulating layer 111b between a free magnetic layer 111a and a fixed magnetic layer 111c), and
Baek does not disclose:
a conductive layer connecting the magnetization fixed layer to the storage layer.
However, Aggarwal teaches:
a conductive layer (Fig. 15: heavy-metal via 1103; [0092]) connecting the magnetization fixed layer (Fig. 2A: fixed region 204; [0044]) to the storage layer (free region 202; [0044]. Examiner notes that MTJ bits 1108, 1100, 1112 each contain these layers).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Aggarwal to Baek wherein the magnetoresistive storage element includes a conductive layer connecting the magnetization fixed layer to the storage layer in order to implement a higher-density, lower-cost memory with an MTJ cell that has greater longevity (Aggarwal, [0052]).
Regarding claim 10, Baek and Aggarwal together disclose the limitations of claim 2, and further through Aggarwal:
wherein the conductive layer (Fig. 15: 1103) is formed on an outer peripheral
surface of the magnetoresistive storage element (1108) to cross the insulating layer (Fig. 2: intermediate region 206; [0044]).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Baek (US Pub. 20110194338 A1) and Aggarwal (US Pub. 20190221609 A1) as applied to claim 2 above, and further in view of Oka et al. (WO 2020195151 A1; “Oka”) and Dieny et al. (US Pub. 20090290266 A1; “Dieny”).
Regarding claim 3, Baek and Aggarwal together disclose the limitations of claim 2, and further through Baek:
wherein the write unit (Fig. 1A: 119) causes the blow current to flow through the magnetoresistive storage element ([0042]) to
Neither Baek nor Aggarwal discloses:
destroy the conductive layer and bring the conductive layer into a non-conductive state.
However, Oka teaches:
destroy the conductive layer and bring the conductive layer into a non-conductive state ([0046]: Here, the second blow voltage Vblow2 is set to a voltage that flows a second blow current Iblow2 of a magnitude necessary to destroy the upper electrode 14 and lower electrode 15 of the filament 16. Examiner asserts that the electrodes are conductive layers and that destroying them brings them into a non-conductive state. Examiner concedes that the electrodes of Oka are not the same as a conductive layer as claimed in claim 2, upon which claim 3 depends).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Oka to modified Baek wherein the write unit destroys the conductive layer and brings the conductive layer into a non-conductive state in order to increase the capacity of the storage elements and reduce their number by using multi-level storage (Oka, [0015]).
Also, through Dieny:
the conductive layer ([0036]: the dielectric or semiconducting layer with the electrically conducting bridges may be made by placing an insulating layer with discontinuities between two electrically conducting layers in the stack and by making the electrically conducting material diffuse through discontinuities in the insulating layer. The discontinuities may exist naturally in the insulating layer or they may be created artificially in the insulating layer; [0123]: The oxide layer may comprise discontinuities naturally…All that is necessary is to deposit the oxides layer on a metallic support…The electrically conducting bridges are then formed naturally)
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Dieny to modified Baek wherein there is a conductive layer in order to implement a magnetoresistive spin valve device that has high magnetoresistance and a junction resistance similar to that of prior art (Dieny, [0014]).
Claims 4-5 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Baek (US Pub. 20110194338 A1) and Aggarwal (US Pub. 20190221609 A1) as applied to claim 2 above, and further in view of Oka (WO 2020195151 A1).
Regarding claim 4, Baek and Aggarwal together disclose the limitations of claim 2, and further through Baek:
wherein the write unit (Fig. 1A: 119) causes the blow current to flow through the magnetoresistive storage element ([0042]) to
Neither Baek nor Aggarwal discloses:
destroy the insulating layer and bring the insulating layer into a conductive state.
However, Oka teaches:
destroy the insulating layer and bring the insulating layer into a conductive state ([0044]: As a result, a first blow current Iblow1, whose magnitude corresponds to the height of the first blow voltage Vblow1, flows through the memory element 10 only for the duration of the first blow time Tblow1. Here, the first blow voltage Vblow1 is set to a voltage that allows a first blow current Iblow1 to flow, which is of a magnitude necessary to destroy only the tunnel barrier layer 13 of the filament 16).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Oka to modified Baek wherein the write unit destroys the insulating layer and brings the insulating layer into a conductive state in order to increase the capacity of the storage elements and reduce their number by using multi-level storage (Oka, [0015]).
Regarding claim 5, Baek and Aggarwal together disclose the limitations of claim 2, and further through Baek:
wherein the write unit (Fig. 1A: 119) causes the blow current to flow through the magnetoresistive storage element ([0042]) to
Neither Baek nor Aggarwal discloses:
wherein the magnetoresistive storage element further includes a connection layer laminated on the magnetization fixed layer or the storage layer, and
destroy the connection layer and bring the connection layer into a non-conductive state.
However, Oka teaches:
wherein the magnetoresistive storage element further includes a connection layer laminated on the magnetization fixed layer or the storage layer (Fig. 2: electrodes 14 and 15; [0110]: an upper electrode 14 formed on the magnetized fixed layer 12, a memory layer 11, a lower electrode 15 formed on the memory layer 11), and
destroy the connection layer and bring the connection layer into a non-conductive state ([0131]: Here, the second writing voltage Vfuse2 is set to a voltage high enough to allow a second blow current Iblow2, which is large enough to destroy the upper electrode 14 and lower electrode 15 of the filament 16, to flow through the memory element 10).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Oka to modified Baek wherein the magnetoresistive storage element further includes a connection layer laminated on the magnetization fixed layer or the storage layer, and destroy the connection layer and bring the connection layer into a non-conductive state in order to increase the capacity of the storage elements and reduce their number by using multi-level storage (Oka, [0015]).
Regarding claim 7, Baek and Aggarwal together disclose the limitations of claim 2. Baek teaches four resistance states. Neither Baek nor Aggarwal discloses:
wherein the four resistance states include a resistance state in which the insulating layer is destroyed and is in a conductive state.
However, Oka teaches:
wherein the four resistance states include a resistance state in which the insulating layer is destroyed and is in a conductive state ([0052]: As shown in Figure 4, for example, in the first state, which is the initial state of the filament 16, it can be seen that there is variation in the resistance value R0 of the filament 16. Then, in the first state, when the tunnel barrier layer 13 constituting the filament 16 is destroyed by the first blow current Iblow1, the resistance state changes from the first state to the second state, as shown in Figure 4. Since the tunnel barrier layer 13 is an insulating layer, after the tunnel barrier layer 13 is destroyed, the resistance value R changes from resistance value R0 to resistance value R1 (R1 < R0). In other words, the resistance value decreases compared to the first state (low resistance state)).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Oka to modified Baek wherein the four resistance states include a resistance state in which the insulating layer is destroyed and is in a conductive state in order to increase the capacity of the storage elements and reduce their number by using multi-level storage (Oka, [0015]).
Regarding claim 8, Baek and Aggarwal together disclose the limitations of claim 2. The first limitation of claim 8 is exactly the same as the first limitation of claim 5, and is thus rejected for the same reasons. Also, Baek teaches four resistance states. Neither Baek nor Aggarwal discloses:
the four resistance states include a resistance state in which the connection layer is destroyed and is in a non- conductive state.
However, Oka teaches:
the four resistance states include a resistance state in which the connection layer is destroyed and is in a non- conductive state (Subsequently, in the second state, when the upper electrode 14 and lower electrode 15 constituting the filament 16 are destroyed by the second blow current Iblow2, the resistance state changes from the second state to the third state, as shown in Figure 5. In this case, the electrodes are destroyed, causing the resistance R to change significantly from resistance R1 to resistance R2 (R2 >> R1). In other words, the resistance value increases significantly compared to the second state (high resistance state). Furthermore, the third state is a state in which the resistance value is higher than that of the first state).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Oka to modified Baek wherein the four resistance states include a resistance state in which the connection layer is destroyed and is in a non- conductive state in order to increase the capacity of the storage elements and reduce their number by using multi-level storage (Oka, [0015]).
Claims 12, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Baek (US Pub. 20110194338 A1) as applied to claim 1 above, and further in view of Oka (WO 2020195151 A1).
Regarding claim 12, Baek discloses the limitations of claim 1. Baek does not disclose:
wherein the write unit changes a magnitude of the blow current to change the magnetoresistive storage element into at least two identifiable resistance states.
However, Oka teaches:
wherein the write unit changes a magnitude of the blow current to change the magnetoresistive storage element into at least two identifiable resistance states ([0052]: in the first state, when the tunnel barrier layer 13 constituting the filament 16 is destroyed by the first blow current Iblow1, the resistance state changes from the first state to the second state, as shown in Figure 4; [0053]: Subsequently, in the second state, when the upper electrode 14 and lower electrode 15 constituting the filament 16 are destroyed by the second blow current Iblow2, the resistance state changes from the second state to the third state, as shown in Figure 5).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Oka to modified Baek wherein the write unit changes a magnitude of the blow current to change the magnetoresistive storage element into at least two identifiable resistance states in order to increase the capacity of the storage elements and reduce their number by using multi-level storage (Oka, [0015]).
Regarding claim 15, Baek discloses the limitations of claim 1. Baek does not disclose:
wherein the write unit changes a magnitude of the blow current using a plurality of power supply voltages having different output voltages.
However, Oka teaches:
wherein the write unit changes a magnitude of the blow current using a plurality of power supply voltages having different output voltages ([0086]: In parallel with this, the control circuit 60 supplies a high-level control signal SW to the gate terminals of the first and second writing switch elements 23 and 24, which connects the upper electrode 14 to ground potential. As a result, a low-level signal Vg from the boost circuit 22 is applied to the gate electrode 21G of the blow transistor 21, and the upper electrode 14 is connected to ground potential. In other words, the first blow current Iblow1 flows through the memory element 10 only during the first blow time Tblow1; [0088]: a low-level signal Vg from the boost circuit 22 is applied to the gate electrode 21G of the blow transistor 21, and the upper electrode 14 is connected to ground potential. In other words, the second blow current Iblow2 flows through the memory element 10 only during the second blow time Tblow2).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Oka to modified Baek wherein the write unit changes a magnitude of the blow current using a plurality of power supply voltages having different output voltages in order to increase the capacity of the storage elements and reduce their number by using multi-level storage (Oka, [0015]).
Regarding claim 16, Baek discloses the limitations of claim 1. Baek does not disclose:
wherein the write unit includes a plurality of transistors connected in parallel and changes conduction and non-conduction of each of the plurality of transistors to change a magnitude of the blow current.
However, Oka teaches:
wherein the write unit includes a plurality of transistors connected in parallel (Fig. 2: writing switch elements 23 and 24; [0025]) and changes conduction and non-conduction of each of the plurality of transistors to change a magnitude of the blow current ([0086]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Oka to modified Baek wherein the write unit includes a plurality of transistors connected in parallel and changes conduction and non-conduction of each of the plurality of transistors to change a magnitude of the blow current in order to increase the capacity of the storage elements and reduce their number by using multi-level storage (Oka, [0015]).
Claims 6 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Baek (US Pub. 20110194338 A1) and Aggarwal (US Pub. 20190221609 A1) as applied to claim 2 above, and further in view of Hoenigschmid et al. (DE 102007006567 B3; “Hoenigschmid”).
Regarding claim 6, Baek and Aggarwal together disclose the limitations of claim 2. Baek teaches four resistance states. Neither Baek nor Aggarwal discloses:
a resistance state in which the conductive layer is destroyed and is in a non- conductive state.
However, Hoenigschmid teaches:
a resistance state in which the conductive layer is destroyed and is in a non- conductive state ([0030]: The switching mechanism is based on the polarity-dependent electrochemical deposition and removal of metal in a thin solid electrolyte layer…This leads to the formation of metal-containing accumulations that form a conductive bridge…Once a continuous ion pathway has been formed, this pathway can short-circuit the otherwise high-resistance solid electrolyte between two electrodes, thereby reducing the effective electrical resistance. In this way, two different resistance states can be written into such a CBRAM memory element by means of a bidirectional programming current).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Hoenigschmid to modified Baek wherein the four resistance states include a resistance state in which the conductive layer is destroyed and is in a non-conductive state in order to implement a resistive memory cell that optimizes the current flow through the cell (Hoenigschmid, [0010]).
Regarding claim 9, Baek, Aggarwal, and Hoenigschmid together disclose the limitations of claim 6. Baek teaches four resistance states. The other subject matter of claim 9, included below, is known to one possessing ordinary knowledge in the art. MRAM cell functioning includes both parallel and antiparallel orientations by default.
a resistance state in which the magnetization direction of the magnetization fixed layer and the magnetization direction of the storage layer are parallel to each other, and a resistance state in which the magnetization direction of the magnetization fixed layer and the magnetization direction of the storage layer are antiparallel to each other.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Baek (US Pub. 20110194338 A1) and Aggarwal (US Pub. 20190221609 A1) as applied to claim 2 above, and further in view of Nakayama et al. (US Pub. 20150069557 A1; “Nakayama”).
Regarding claim 11, Baek and Aggarwal together disclose the limitations of claim 2. Neither Baek nor Aggarwal discloses:
wherein the conductive layer is a degenerated layer of one or both of the magnetization fixed layer and the storage layer.
However, Nakayama teaches:
wherein the conductive layer is a degenerated layer of one or both of the magnetization fixed layer and the storage layer ([0042]: the ions 108 are implanted not only into the damage layer generated on the storage layer 104 but into the damage layers generated on the lower electrode 101, the reference layer 102, the tunnel barrier layer 103, the cap layer 105 and the upper electrode 106. As a result, implantation regions 109 are formed also on the surfaces of the lower electrode 101, the reference layer 102, the tunnel barrier layer 103, the cap layer 105 and the upper electrode 106. Examiner notes that there are damaged areas on both of the reference layer 102, which is analogous to the magnetization fixed layer, and the storage layer 104).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Nakayama to modified Baek wherein the conductive layer is a degenerated layer of one or both of the magnetization fixed layer and the storage layer in order to use a spin injection write scheme for MTJs to achieve MJTs that are small and use a low electric current (Nakayama, [0008]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Baek (US Pub. 20110194338 A1) as applied to claim 1 above, and further in view of Yu (US Pub. 20210257545 A1).
Regarding claim 13, Baek discloses the limitations of claim 1. Baek does not disclose:
wherein the magnetoresistive storage element is an element that can be changed to five identifiable resistance states, and
the write unit changes the magnetoresistive storage element into the five identifiable resistance states by changing the magnetization direction of the magnetoresistive storage element or causing the blow current to flow through the magnetoresistive storage element.
However, Yu teaches:
wherein the magnetoresistive storage element is an element that can be changed to five identifiable resistance states ([0077]: When all parts of the MTJ 501 have the parallel magnetization states and all parts of the MTJ 502 have the anti-parallel magnetization states, it represents the fifth electrical resistance state), and
the write unit changes the magnetoresistive storage element into the five identifiable resistance states by changing the magnetization direction of the magnetoresistive storage element ([0077]) or causing the blow current to flow through the magnetoresistive storage element.
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Yu to modified Baek wherein the magnetoresistive storage element is an element that can be changed to five identifiable resistance states, and the write unit changes the magnetoresistive storage element into the five identifiable resistance states by changing the magnetization direction of the magnetoresistive storage element or causing the blow current to flow through the magnetoresistive storage element in order to implement an SOT-MRAM structure that can represent eight memory levels (Yu, [0063] & [0072]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Baek (US Pub. 20110194338 A1) and Yu (US Pub. 20210257545 A1) as applied to claim 13 above, and further in view of Oka (WO 2020195151 A1).
Regarding claim 14, Baek and Yu together disclose the limitations of claim 13. Neither Baek nor Yu discloses:
wherein the write unit changes a magnitude of the blow current to change the magnetoresistive storage element into three identifiable resistance states.
However, Oka teaches:
wherein the write unit changes a magnitude of the blow current to change the magnetoresistive storage element into three identifiable resistance states ([0103]: the resistance state of the filament 16 can be set to one of three states (first state, second state, and third state) by changing the blowing conditions of the memory element 10).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Oka to modified Baek wherein the write unit changes a magnitude of the blow current to change the magnetoresistive storage element into three identifiable resistance states in order to increase the capacity of the storage elements and reduce their number by using multi-level storage (Oka, [0015]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Baek (US Pub. 20110194338 A1) as applied to claim 1 above, and further in view of Tang et al. (US Pub. 20050083747 A1; “Tang”).
Regarding claim 17, Baek discloses the limitations of claim 1. Baek does not disclose:
a read unit that reads a voltage related to a resistance value of the magnetoresistive storage element, wherein
the read unit includes
a generation unit that generates a plurality of reference voltages to determine the at least four identifiable resistance states, and
a determination unit that compares the voltage with the plurality of reference voltages and determines the at least four identifiable resistance states.
However, Tang teaches:
a read unit that reads a voltage related to a resistance value of the magnetoresistive storage element ([0006]: The sense voltage V.sub.sense 80 is compared within the comparator 55 with the reference voltage V.sub.REF 75 to determine the state of the digital data retained within the MTJ device 15), wherein
the read unit (Fig. 9: reference generator 400 and comparators 450, 455, and 460; [0055]-[0056]) includes
a generation unit (Fig. 9: 400) that generates a plurality of reference voltages to determine the at least four identifiable resistance states ([0038]: Referring now to FIG. 4, the representation of the four cell resistance states will generate the four read currents I.sub.RD1 150a, I.sub.RD2 150b, I.sub.RD3 150c, and I.sub.RD4 150d. The multilevel reference source must provide reference currents…that have magnitudes that are midway between the magnitudes of the four read currents), and
a determination unit (450, 455, 460) that compares the voltage with the plurality of reference voltages ([0006]: The sense voltage V.sub.sense 80 is compared within the comparator 55 with the reference voltage V.sub.REF 75 to determine the state of the digital data retained within the MTJ device 15) and determines the at least four identifiable resistance states ([0038]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Tang to modified Baek wherein the storage device comprises a read unit that reads a voltage related to a resistance value of the magnetoresistive storage element, wherein the read unit includes a generation unit that generates a plurality of reference voltages to determine the at least four identifiable resistance states, and a determination unit that compares the voltage with the plurality of reference voltages and determines the at least four identifiable resistance states in order to implement a reference generator with multiple levels that can track nonlinear resistive elements (Tang, [0019]-[0020]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Baek (US Pub. 20110194338 A1) and Tang (US Pub. 20050083747 A1) as applied to claim 17 above, and further in view of Yu (US Pub. 20210257545 A1).
Regarding claim 18, Baek and Tang together disclose the limitations of claim 17. Further, through Tang:
the generation unit (Fig. 9: 400) generates a plurality of reference voltages to determine the identifiable resistance states ([0038]), and the determination unit (450, 455, 460) compares the voltage with the plurality of reference voltages and determines the identifiable resistance states ([0006]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Tang to modified Baek wherein the generation unit generates a plurality of reference voltages to determine the identifiable resistance states, and the determination unit compares the voltage with the plurality of reference voltages and determines the identifiable resistance states in order to implement a reference generator with multiple levels that can track nonlinear resistive elements (Tang, [0019]-[0020]).
Neither Baek nor Tang discloses:
wherein the magnetoresistive storage element is an element that changes to five identifiable resistance states,
However, Yu teaches:
wherein the magnetoresistive storage element is an element that changes to five identifiable resistance states ([0077]),
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Yu to modified Baek wherein the magnetoresistive storage element is an element that changes to five identifiable resistance states in order to implement an SOT-MRAM structure that can represent eight memory levels (Yu, [0063] & [0072]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIZABETH ROSE AGGER whose telephone number is (571)270-0250. The examiner can normally be reached Mon-Fri, 8am-5pm.
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/E.R.A./Examiner, Art Unit 2824
6/26/2026
/PHO M LUU/Primary Examiner, Art Unit 2824
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