DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 08, 2026 has been entered.
Status of the Claims
Group I was elected.
Amendment filed January 08, 2026 is acknowledged. Claims 1, 3 and 8 have been amended. Non-elected Invention, Group II, Claims 10-15 have been withdrawn from consideration. Claims 1-15 are pending.
Action on merits of Elected Invention, Group I, claims 1-9 follows.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on January 08, 2026 was filed after the mailing date of the Office Action on November 25, 2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by HSIEH et al. (US. Patent No. 5,907,169) of record.
With respect to claim 1, HSHIEH ‘169 teaches a power semiconductor device as claimed including:
- a semiconductor body with a top side,
- a main electrode (source electrode) on the top side and
- a gate electrode (230) on the top side and arranged next to the main electrode in a first lateral direction, the gate electrode (230) is electrically isolated from the semiconductor body by an electrically isolating material (132), wherein
- the semiconductor body comprises
- a drift layer (210) of a first conductivity type (N),
- a base region (240) of a second conductivity type (P) arranged vertically between the drift layer (210) and the top side,
- a contact region (225’) of the first conductivity type arranged vertically between the drift layer (210) and the top side, wherein the contact region (225’) adjoins the base region (240) and the top side,
- a drift region (212) of the first conductivity type (N) arranged next to the base region (240) in the first lateral direction and adjoining the base region (240),
- the main electrode is in electrical contact with the contact region (225’),
- in plan view of the top side, the gate electrode (230) at least partially covers a channel portion of the base region (240) which lies, in the first lateral direction, between the contact region (225’) and the drift region (212),
- at the top side, the drift region (212) projects beyond the base region (240) in vertical direction,
- in plan view of the top side, an entirety of the gate electrode (230) is disposed outside of the drift region (212), and
wherein the drift region (212) is epitaxially grown and projects beyond the base region (240) by at least 50 nm to reduce parasitic gate/drain capacitance. (See FIGs. 5A, 7).
Regarding the term “to reduce parasitic gate/drain capacitance”, this is a function of the drift region that is projected beyond the base region.
Since the drift region 212 of HSHIEH is epitaxially grown and projects beyond the base region, to reduce parasitic gate/drain capacitance is inherently resulted.
With respect to claim 2, at least one of the contact region (225’) and the drift region (212) of HSIEH is grown epitaxially.
With respect to claim 3, at least one of the epitaxially grown regions of HSIEH has
- an inverted doping profile with a doping concentration decreasing in a direction pointing from an interior of the semiconductor body towards the top side or
- a homogenous doping profile.
With respect to claim 4, the contact region (225’) and the channel portion of HSIEH at least partially overlap with each other when viewed along the first lateral direction.
With respect to claim 5, the drift region (212) of HSIEH has a greater doping concentration than the drift layer (210).
With respect to claim 6, in plan view of the top side, the gate electrode (230) of HSIEH partially covers the contact region (225’).
With respect to claim 7, the power semiconductor device of HSIEH is a MOSFET or an IGBT or a MISFET.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 8, is rejected under 35 U.S.C. 103 as being unpatentable over HSIEH ‘169 as applied to claim 1 above, and further in view of HUANG (CN pub. No. 109244119) of record.
HSIEH teaches the power semiconductor device as described in claim 1 above including the semiconductor body is based on Si, and the drift region (115) projects beyond the base region (140) by at least 50 nm to reduce parasitic gate/drain capacitance.
Thus, HSIEH is shown to teach all the features of the claim with the exception of explicitly disclosing the semiconductor body being based on SiC.
However, HUANG teaches a power semiconductor device utilizing a semiconductor body based on SiC having a bandgap wider than silicon.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the power semiconductor device of HSIEH utilizing the wide-bandgap semiconductor as taught by HUANG to provide for a MOS device having higher avalanche resistance.
Moreover, given a finite number of materials and their compounds, it is obvious to try without undue experimentation.
Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416., 125 USPQ 416.
Claims 9 is rejected under 35 U.S.C. 103 as being unpatentable over HSIEH ‘169 as applied to claim 1 above, and further in view of KOJIMA et al. (US. Pub. No. 2005/0230686).
HSIEH teaches the power semiconductor device as described in claim 1 above including the gate electrode (230) projecting beyond the base region (240) at least partially overlap with each other when viewed along the first lateral direction.
Thus, HSIEH is shown to teach all the features of the claim with the exception of explicitly disclosing the contact region projecting beyond the base region.
However, KOJIMA teaches a power semiconductor device including gate electrode (8) and the contact region (4b) projecting beyond the base region (3b) at least partially overlap with each other when viewed along the first lateral direction. (See FIG. 1).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the semiconductor device of HSIEH having the gate electrode and the contact region projecting beyond the base region as taught by KOJIMA to improve channel mobility.
Response to Arguments
Applicant's arguments filed January 08, 2026 have been fully considered but they are not persuasive.
Rejection Under 35 USC § 102
Applicant argues:
The amended limitation "in plan view of the top side, an entirety of the gate electrode is disposed outside of the drift region," as recited by amended claim 1, requires complete absence of overlap between the gate electrode and drift region in plan view, which is not disclosed or suggested by HSIEH '169.
However, as shown in FIG. 7, the entirety of the gate electrode 230 of HSIEH ‘169 is clearly disposed outside of the drift region 212.
Note that, the invention also includes the gate electrode 3 overlapping the drift region 10 as shown in FIG. 2.
Applicant also argues:
The specification supports this amendment by explaining that the raised projecting drift region enables the gate electrode to be formed such that it does not completely overlap with the drift region, thereby significantly reducing parasitic capacitance. This non-overlapping configuration represents a distinct structural arrangement that is not taught by HSIEH'169.
Indeed, HSIEHI'169 fails to disclose that the drift region projects beyond the base region to reduce parasitic gate/drain capacitance' as recited in claim 1.
That is, HSIEH '169 does not teach or suggest the specific functional relationship between the projecting drift region and capacitance reduction, which is a critical distinguishing feature of the claimed invention's device concept based on raised source and/or drift regions.
Note that, the specification also support for gate electrode overlapping the drift region and providing the same function of “reduce parasitic gate/drain capacitance”.
There is no requirement that the “function” of an element must be disclosed.
“Function” is an inherent characteristic of a structure.
For instant, a function of a gate electrode is to control the formation of the channel.
Does that mean without disclosing the “function of control a channel” the gate electrode of a reference being disqualified as a “gate electrode”?
Rejection Under 35 USC § 103
With respect to claim 8, applicant argues: “particularly that HSIEH’s drift region 212 does not project beyond the base region in the manner claimed”.
However, as shown the drift region 212 of HSIEH ‘169 clearly project beyond the base region 240 in the manner claimed.
Regarding “semiconductor body is based on SiC”, Applicant argues: HUANG does not disclose specific structural feature recited.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Note that, the structural features are fully disclosed by HSIEH.
Indeed, Applicant acknowledged that HUANG merely teaches using wide-bandgap material like SiC.
The limitations are met.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH D MAI whose telephone number is (571)272-1710 (Email: Anh.Mai2@uspto.gov). The examiner can normally be reached 10:00-4:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue A Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANH D MAI/ Primary Examiner, Art Unit 2893