DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The Amendment filed on 09/10/2026 has been received and entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 5-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oh et al. (US 10,643,704, hereinafter "Oh").
Regarding claim 1, Oh (Fig. 6) shows a memory device comprising:
a first semiconductor layer (C) including a memory cell array, the memory cell array connected to a plurality of word lines extending in a first direction (FD) and a plurality of bit lines extending in a second direction substantially perpendicular to the first direction (SD), the memory cell array including a first memory group ((110-1) and a second memory group (110-2) arranged in the first direction; and
a second semiconductor layer (P) disposed under the first semiconductor layer and including a pair of a first areas (130-1 and 130-2 and the blank areas) overlapping the first memory group and the second memory group in a third direction (TD) substantially perpendicular to the first direction and the second direction and a second area (122A, 121 and 122B) disposed between the pair of first areas and overlapping the first area in the first direction;
the second semiconductor layer comprising:
a row decoder (Fig. 4, 120 including 122A, 121 and 122B) disposed in the second area, and including a plurality of pass transistors (121); and
a first voltage switching circuit (122A) configured to transmit an operating voltage to the plurality of pass transistors and including a plurality of switching elements, wherein at least one switching element among the plurality of switching elements is disposed in the second area to overlap the plurality of pass transistors in the first direction (Fig. 4 and Fig. 5, at least one switching element in 122A is disposed in the second area to overlap the plurality of pass transistors 121 in the direction FD).
Regarding claim 2, Oh discloses the memory device according to claim 1, further comprising:
a page buffer circuit (130-1) disposed in the pair of first areas, and connected to the plurality of bit lines;
wherein the at least one switching element overlaps the page buffer circuit in the first direction.
Regarding claim 3. Oh discloses the memory device according to claim 2,
wherein each of the pair of first areas includes a first under cell area (130-1) where the page buffer circuit is disposed and a second under cell area (the blank area on the left side of 121) overlapping the first under cell area in the second direction, and
wherein the at least one switching element overlaps the first under cell area in the first direction.
Regarding claim 5, Oh discloses the memory device according to claim 1,
wherein the plurality of switching elements include a first switching element configured to output an unselected global word line voltage to a global word line and a second switching element configured to output a selected global word line voltage to a global word line, and
wherein the first switching element overlaps the plurality of pass transistors in the first direction (Fig. 4 and Fig. 5).
Regarding claim 6, Oh discloses the memory device according to claim 1, further comprising:
a page buffer circuit (130-1) disposed in the pair of first areas and connected to the plurality of bit lines;
wherein each the first area includes a first under cell area (130-1) where the page buffer circuit is disposed and a second under cell area (the blank area on the left side of 121) overlapping the first under cell area in the second direction; and
wherein the at least one switching element overlaps the first under cell area and the second under cell area in the first direction.
Regarding claim 7, Oh (Fig. 6) shows the memory device according to claim 6, wherein a length in the second direction of an area where the at least one switching element (122A and 122B) overlaps the plurality of pass transistors (121) in the first direction is the same as a sum of a length in the second direction of the first under cell area and a length in the second direction of the second under cell area (the length of 121 in the second direction).
Regarding claim 8, Oh discloses the memory device according to claim 6, further comprising:
a second voltage switching circuit (122B) disposed in the pair of first areas and configured to transmit an unselected global word line voltage and a selected global word line voltage to the first voltage switching circuit;
wherein the second voltage switching circuit overlaps the at least one switching element in the first direction (Fig. 4).
Regarding claim 9, Oh discloses the memory device according to claim 1, further comprising:
a page buffer circuit (130-1) disposed in the pair of first areas and connected to the plurality of bit lines;
wherein the first area includes a first under cell area (130-1) where the page buffer circuit is disposed and a second under cell area overlapping the first under cell area in the second direction (a blank area under 130-1), and
wherein at least the other one of the plurality of switching elements (122B) is disposed in an area of the second area (122B) except an area overlapping the first under cell area in the first direction and an area overlapping the second under cell area in the first direction (121 and 122A).
Regarding claim 10, Oh (Fig. 6) shows a memory device comprising:
a first semiconductor layer including a memory cell array, the memory cell array connected to a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction substantially perpendicular to the first direction, the memory cell array including a first memory group and a second memory group arranged in the first direction; and
a second semiconductor layer disposed under the first semiconductor layer, and including a pair of first areas (130-1 and 130-2) overlapping the first memory group and the second memory group in a third direction substantially perpendicular to the first direction and the second direction and a second area (122A, 121 and 122B) disposed between the pair of the first areas and overlapping the first area in the first direction;
the second semiconductor layer comprising:
a page buffer circuit (130-1 or 130-2) disposed in the pair of first areas and connected to the plurality of bit lines;
a row decoder (120) disposed in the second area, and including a plurality of pass transistors (121); and
a first voltage switching circuit configured to transmit an operating voltage to the plurality of pass transistors and including a plurality of switching elements, wherein at least one switching element among the plurality of switching elements is disposed in the second area to overlap the page buffer circuit in the first direction (Fig. 4 and Fig. 5).
Regarding claim 11, Oh discloses the memory device according to claim 10,
Wherein each of the pair of first areas includes a first under cell area where the page buffer circuit is disposed and a second under cell area overlapping the first under cell area in the second direction; and
wherein the at least one switching element overlaps the first under cell area in the first direction (see the rejection of claim 3).
Regarding claim 12, Oh discloses the memory device according to claim 10, wherein the plurality of switching elements include a first switching element configured to output an unselected global word line voltage to a global word line and a second switching element configured to output a selected global word line voltage to a global word line; and
wherein the first switching element overlaps the plurality of pass transistors in the first direction (see the rejection of claim 5).
Regarding claim 13. Oh discloses the memory device according to claim 12, wherein the first switching element is located on the same line as at least one of the plurality of pass transistors in the first direction (Fig. 4).
Regarding claim 14, Oh discloses the memory device according to claim 10,
wherein each of the pair of first areas includes a first under cell area where the page buffer circuit is disposed and a second under cell area overlapping the first under cell area in the second direction; and
wherein the at least one switching element overlaps the first under cell area and the second under cell area in the first direction (see the rejection of claim 6).
Regarding claim 15, Oh (Fig. 6 and the rejection of claim 10) discloses a memory device comprising:
a first semiconductor layer including a memory cell array, the memory cell array connected to a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction substantially perpendicular to the first direction; and
a second semiconductor layer disposed under the first semiconductor layer, the second semiconductor layer comprising:
a page buffer circuit connected to the plurality of bit lines;
a row decoder connected to the plurality of word lines, and including a plurality of pass transistors; and
a first voltage switching circuit configured to transmit an operating voltage to the plurality of pass transistors and including a plurality of switching elements, wherein at
least one switching element among the plurality of switching elements is disposed between the plurality of pass transistors to overlap the plurality of pass transistors in the first direction.
Regarding claim 16, Oh (Fig. 6) shows the memory device according to claim 15, wherein the at least one switching element (122B) overlaps the page buffer circuit (130- 1) in the first direction.
Regarding claim 17, Oh (Fig. 6) shows the memory device according to claim 15, wherein a length in the second direction of an area where the at least one switching element (122B) overlaps the plurality of pass transistors in the first direction is smaller than a length in the second direction of an area where the row decoder is disposed (the length of 121).
Regarding claim 18. Oh discloses the memory device according to claim 15, wherein a length in the second direction of an area where the at least one switching element (122A and 122B) overlaps the plurality of pass transistors in the first direction is substantially the same as a length in the second direction of an area where the row decoder (the row decoder has a length in the second direction equal to the length of 121) is disposed.
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 09/10/2026 have been fully considered but they are not persuasive.
Applicant stated:
“Oh fails to teach or suggest "a first voltage switching circuit ... wherein at least one switching element among the plurality of switching elements is disposed in the second area" and "a second semiconductor layer disposed under the first semiconductor layer and including a pair of first areas overlapping the first memory group and the second memory group in a third direction substantially perpendicular to the first direction and the second direction and a second area disposed between the pair of first areas and overlapping the pair of first areas in the first direction" as set forth in claim 1 as amended.
In response to Applicant’s arguments, the Examiner point out that Oh does teach “a first voltage switching circuit (Fig. 6, 122A) ... wherein at least one switching element among the plurality of switching elements is disposed in the second area (122A, 121 and 122B) " and "a second semiconductor layer (P) disposed under the first semiconductor layer and including a pair of first areas (130-1 and 130-2 and the blank areas) overlapping the first memory group and the second memory group in a third direction substantially perpendicular to the first direction and the second direction and a second area disposed between the pair of first areas and overlapping the pair of first areas in the first direction (see the rejection of claim 1).
Oh discloses all the limitations of claims 1, 10 and 15 and their corresponding dependent claims as clearly stated in the rejections of claims 1-3 and 5-18 above; therefore, the rejections of claims 1-3 and 5-18 under 35 U.S.C. §102(a)(1) as unpatentable over Oh are maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HUAN HOANG/ Primary Examiner, Art Unit 2827
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