DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 5-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oh et al. (US 10,643,704, hereinafter “Oh”).
Regarding claim 1, Oh (Fig. 6) hows a memory device comprising:
a first semiconductor layer (C) including a memory cell array (110-1 or 110-2), the memory cell array connected to a plurality of word lines extending in a first direction (FD) and a plurality of bit lines extending in a second direction substantially perpendicular to the first direction (SD); and
a second semiconductor layer (P) disposed under the first semiconductor layer, and including a first area (130-1 and 130-2 and the blank areas) overlapping the first semiconductor layer in a third direction (TD) substantially perpendicular to the first direction and the second direction and a second area (122A, 121 and 122B) overlapping the first area in the first direction,
the second semiconductor layer comprising:
a row decoder (120) disposed in the second area, and including a plurality of pass transistors (121); and
a first voltage switching circuit (122A) configured to transmit an operating voltage to the plurality of pass transistors, and including a plurality of switching elements, wherein at least one switching element among the plurality of switching elements is disposed in the second area to overlap the plurality of pass transistors in the first direction (Fig. 4 and Fig. 5).
Regarding claim 2, Oh discloses the memory device according to claim 1, further comprising:
a page buffer circuit (130-1) disposed in the first area, and connected to the plurality of bit lines,
wherein the at least one switching element overlaps the page buffer circuit in the first direction.
Regarding claim 3. Oh discloses the memory device according to claim 2,
wherein the first area includes a first under cell area (130-1) where the page buffer circuit is disposed and a second under cell area (area under 130-1 in the second direction) overlapping the first under cell area in the second direction, and
wherein the at least one switching element overlaps the first under cell area in the first direction.
Regarding claim 5, Oh discloses the memory device according to claim 1,
wherein the plurality of switching elements include a first switching element configured to output an unselected global word line voltage to a global word line and a second switching element configured to output a selected global word line voltage to a global word line, and
wherein the first switching element overlaps the plurality of pass transistors in the first direction (Fig. 4 and Fig. 5).
Regarding claim 6, Oh discloses the memory device according to claim 1, further comprising:
a page buffer circuit (130-1) disposed in the first area, and connected to the plurality of bit lines,
wherein the first area includes a first under cell area (130-1) where the page buffer circuit is disposed and a second under cell area (area below 130-1) in the second direction) overlapping the first under cell area in the second direction, and wherein the at least one switching element overlaps the first under cell area and the second under cell area in the first direction.
Regarding claim 7, Oh (Fig. 6) shows the memory device according to claim 6, wherein a length in the second direction of an area where the at least one switching element (122A and 122B) overlaps the plurality of pass transistors (121) in the first direction is the same as a sum of a length in the second direction of the first under cell area and a length in the second direction of the second under cell area (the length of 121 in the second direction).
Regarding claim 8, Oh discloses the memory device according to claim 6, further comprising:
a second voltage switching circuit (122B) disposed in the first area, and configured to transmit an unselected global word line voltage and a selected global word line voltage to the first voltage switching circuit,
wherein the second voltage switching circuit overlaps the at least one switching element in the first direction (Fig. 4).
Regarding claim 9, Oh discloses the memory device according to claim 1, further comprising:
a page buffer circuit (130-1) disposed in the first area, and connected to the plurality of bit lines, wherein the first area includes a first under cell area (130-1) where the page buffer circuit is disposed and a second under cell area overlapping the first under cell area in the second direction (a blank area under 130-1), and
wherein at least the other one of the plurality of switching element (122B) is disposed in an area of the second area (122B) except an area overlapping the first under cell area in the first direction and an area overlapping the second under cell area in the first direction (121 and 122A).
Regarding claim 10, Oh (Fig. 6) shows a memory device comprising:
a first semiconductor layer including a memory cell array, the memory cell array connected to a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction substantially perpendicular to the first direction; and
a second semiconductor layer disposed under the first semiconductor layer, and including a first area (130-1 and 130-2) overlapping the first semiconductor layer in a third direction substantially perpendicular to the first direction and the second direction and a second area (122A, 121 and 122B) overlapping the first area in the first direction,
the second semiconductor layer comprising:
a page buffer circuit (130-1 or 130-2) disposed in the first area, and connected to the plurality of bit lines;
a row decoder (120) disposed in the second area, and including a plurality of pass transistors (121); and
a first voltage switching circuit configured to transmit an operating voltage to the plurality of pass transistors, and including a plurality of switching elements, wherein at least one switching element among the plurality of switching elements is disposed in the second area to overlap the page buffer circuit in the first direction (Fig. 4 and Fig. 5).
Regarding claim 11, Oh discloses the memory device according to claim 10,
wherein the first area includes a first under cell area where the page buffer circuit is disposed and a second under cell area overlapping the first under cell area in the second direction, and
wherein the at least one switching element overlaps the first under cell area in the first direction (see the rejection of claim 3).
Regarding claim 12, Oh discloses the memory device according to claim 10,
wherein the plurality of switching units include a first switching element configured to output an unselected global word line voltage to a global word line and a second switching element configured to output a selected global word line voltage to a global word line, and
wherein the first switching element overlaps the plurality of pass transistors in the first direction (see the rejection of claim 5).
Regarding claim 13. Oh discloses the memory device according to claim 12, wherein the first switching element is located on the same line as at least one of the plurality of pass transistors in the first direction (Fig. 4).
Regarding claim 14, Oh discloses the memory device according to claim 10,
wherein the first area includes a first under cell area where the page buffer circuit is disposed and a second under cell area overlapping the first under cell area in the second direction, and
wherein the at least one switching element overlaps the first under cell area and the second under cell area in the first direction (see the rejection of claim 6).
Regarding claim 15, Oh (Fig. 6 and the rejection of claim 10) discloses a memory device comprising:
a first semiconductor layer including a memory cell array, the memory cell array connected to a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction substantially perpendicular to the first direction; and
a second semiconductor layer disposed under the first semiconductor layer,
the second semiconductor layer comprising:
a page buffer circuit connected to the plurality of bit lines; a row decoder connected to the plurality of word lines, and including a plurality of pass transistors; and
a first voltage switching circuit configured to transmit an operating voltage to the plurality of pass transistors, and including a plurality of switching elements, wherein at least one switching element among the plurality of switching elements is disposed between the plurality of pass transistors to overlap the plurality of pass transistors in the first direction.
Regarding claim 16, Oh (Fig. 6) shows the memory device according to claim 15, wherein the at least one switching element (122B) overlaps the page buffer circuit (130-1) in the first direction.
Regarding claim 17, Oh (Fig. 6) shows the memory device according to claim 15, wherein a length in the second direction of an area where the at least one switching element (122B) overlaps the plurality of pass transistors in the first direction is smaller than a length in the second direction of an area where the row decoder is disposed (the length of 121).
Regarding claim 18. Oh discloses the memory device according to claim 15, wherein a length in the second direction of an area where the at least one switching element (122A and 122B) overlaps the plurality of pass transistors in the first direction is substantially the same as a length in the second direction of an area where the row decoder (the row decoder has a length in the second direction equal to the length of 121) is disposed.
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 1, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “wherein a length in the first direction of a global word line connected to the switching element which is located closest to the second under cell area in the second direction is larger than a length in the first direction of a global word line connected to the switching element which is located farthest from the second under cell area in the second direction.” in combination with the other limitations thereof as is recited in the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUAN HOANG whose telephone number is (571)272-1779. The examiner can normally be reached 7:30AM-4:00PM M-F.
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/HUAN HOANG/Primary Examiner, Art Unit 2827
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