Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 7/21/2026 traverses the 112 rejections which are hereby withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over “Gailus” (US 2016/0150645) in view of “Rubin” (US 2021/0134728).
Regarding claim 1, Gailus discloses 1. A wiring substrate, comprising: an insulating layer having a plurality of through holes (Figs. 8, 14, [0094]-[0096]; the backplane 110 has a plurality of through holes);
a first conductor layer formed on a first surface of the insulating layer (Figs. 8, 14, [0094]-[0096]; a first conductor layer formed on a first surface of the backplane 110);
a second conductor layer formed on a second surface of the insulating layer on an opposite side with respect to the first surface of the insulating layer (Figs. 8, 14, [0094]-[0096]; a second conductor layer formed on a second surface of the insulating layer on an opposite side with respect to the first surface of the backplane 110);
a plurality of interlayer conductors formed in the plurality of through holes of the insulating layer respectively such that the plurality of interlayer conductors is connecting the first and second conductor layers and includes a plurality of first interlayer conductors formed in a first region of the insulating layer and a plurality of second interlayer conductors formed in a second region of the insulating layer at a density that is higher than a density of the plurality of first interlayer conductors formed in the first region (Figs. 8, 14, [0094]-[0096]; vias 630, 632, 634, 636 are first interlayer conductors formed in a first region, vias 1440, 1442, 1450, 1452 are second interlayer conductors formed in a second region at a density higher than the vias in the first region),
wherein the plurality of interlayer conductors is formed such that a thickness of each of the first interlayer conductors is larger than a thickness of each of the second interlayer conductors (Figs. 8, 14, [0094]-[0096]; a thickness of each of the vias 630, 632, 634, 636 are larger that a thickness of each of the vias 1440, 1442, 1450, 1452),
and the insulating layer is formed such that the plurality of through holes includes a plurality of first through holes having the plurality of first interlayer conductors formed therein and a plurality of second through holes having the plurality of second interlayer conductors formed therein and that an inner diameter of each of the first through holes is larger than an inner diameter of each of the second through holes (Figs. 8, 14, [0094]-[0096]; an inner diameter of the respective through holes for each of the vias 630, 632, 634, 636 are larger that an inner diameter of the through holes for each of the vias 1440, 1442, 1450, 1452).
Gallius does not disclose a thickness of each of the first interlayer conductors on an inner wall of the insulating layer surrounding a respective one of the through holes is larger than a thickness of each of the second interlayer conductors on an inner wall of the insulating layer surrounding a respective one of the through holes.
Rubin discloses a thickness of each of the first interlayer conductors on an inner wall of the insulating layer surrounding a respective one of the through holes is larger than a thickness of each of the second interlayer conductors on an inner wall of the insulating layer surrounding a respective one of the through holes (Fig. 3E, [0070]; a thickness of the metallization 344 on the inner wall of the insulating layer 342 is larger than a thickness of each of the metallization 346).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Gailus’ wiring substrate with Rubin’s insulating layer in order to provide an insulating layer for a multi-chip package structures which comprise embedded chip interconnect bridges and fan-out redistribution layers, as well as methods for fabrication such multi-chip package structures, as suggested by Rubin at [0011].
Regarding claim 8, Gailus in view of Rubin discloses the claimed invention as applied to claim 1, above.
Gailus discloses 8. The wiring substrate according to claim 1, wherein the insulating layer has a component mounting region formed such that the second region is overlapping with the component mounting region and that the first region is surrounding the second region (Figs. 8, 14, [0094]-[0096]; the second region is overlapping with the component mounting region and that the first region is surrounding the second region).
Claims 2 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Gailus in view of Rubin and “Kimishima ‘107” (US 2021/0259107).
Regarding claim 2, Gailus in view of Rubin discloses the claimed invention as applied to claim 1, above.
Gailus does not disclose the limitations of clam 2.
Kimishima ‘107 discloses 2. The wiring substrate according to claim 1, wherein the plurality of interlayer conductors is formed such that an inner diameter of each of the first interlayer conductors is equal to an inner diameter of each of the second interlayer conductors (Fig. 8, 14, [0040]; an inner diameter (D3) of each of the third through holes 23 and an inner diameter (D1) of each of the first through holes 21 are equal).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Gailus’ wiring substrate, as modified by Rubin, with Kimishima 107’s insulating layer in order for miniaturization and desired electrical characteristics of a wiring substrate to have high reliability in insulation, as suggested by Kimishima ‘107 at [0027].
Regarding claim 14, Gailus in view of Rubin and Kimishima ‘107 discloses the claimed invention as applied to claim 2, above.
Gailus discloses 14. The wiring substrate according to claim 2, wherein the insulating layer has a component mounting region formed such that the second region is overlapping with the component mounting region and that the first region is surrounding the second region (Figs. 8, 14, [0094]-[0096]; the second region is overlapping with the component mounting region and that the first region is surrounding the second region).
Claims 3, 9-10, 12-13, 15, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Gailus in view of Rubin, Kimishima ‘107 and “Kimishima” (US 2022/0104353).
Regarding claim 3, Gailus in view of Rubin discloses the claimed invention as applied to claim 1, above.
Gailus does not disclose the limitations of clam 3.
Kimishima ‘107 discloses an inner diameter of each of the first interlayer conductors is equal to an inner diameter of each of the second interlayer conductors (Fig. 8, 14, [0040]; an inner diameter (D3) of each of the third through holes 23 and an inner diameter (D1) of each of the first through holes 21 are equal).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Gailus’ wiring substrate, as modified by Rubin, with Kimishima 107’s insulating layer in order for miniaturization and desired electrical characteristics of a wiring substrate to have high reliability in insulation, as suggested by Kimishima ‘107 at [0027].
Kimishima Fig. 3A, [0045], discloses the thickness T5 of the interlayer connection conductors 51, 51 are adjustable.
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Gailus’ wiring substrate, as modified by Rubin and Kimishima ‘107, with Kimishima’s adjustable thickness of the interlayer conductors in order for a wiring rule to be applied,, as suggested by Kimishima at [0045]. Since the inner diameter of each of the first and second interlayer conductors are equal, the difference between the diameter of the first and second through holes would be twice a difference between the thickness of the first and second through holes.
Regarding claim 9, Gailus in view of Rubin and Kimishima ‘107 discloses the claimed invention as applied to claim 2, above.
Gailus does not discloses the limitations of claim 9.
Kimishima ‘107 discloses an inner diameter of each of the first interlayer conductors is equal to an inner diameter of each of the second interlayer conductors (Fig. 8, 14, [0040]; an inner diameter (D3) of each of the third through holes 23 and an inner diameter (D1) of each of the first through holes 21 are equal).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Gailus’ wiring substrate, as modified by Rubin, with Kimishima 107’s insulating layer in order for miniaturization and desired electrical characteristics of a wiring substrate to have high reliability in insulation, as suggested by Kimishima ‘107 at [0027].
Kimishima Fig. 3A, [0045], discloses the thickness T5 of the interlayer connection conductors 51, 51 are adjustable.
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Gailus’ wiring substrate, as modified by Rubin and Kimishima ‘107, with Kimishima’s adjustable thickness of the interlayer conductors in order for a wiring rule to be applied,, as suggested by Kimishima at [0045]. Since the inner diameter of each of the first and second interlayer conductors are equal, the difference between the diameter of the first and second through holes would be twice a difference between the thickness of the first and second through holes.
Regarding claim 10, Gailus in view of Rubin and Kimishima ‘107 discloses the claimed invention as applied to claim 2, above.
Gailus does not discloses the limitations of claim 10.
Kimishima discloses the insulating layer is formed such that the inner diameter of each of the first through holes is in a range of 160 μm to 220 μm and that the inner diameter of each of the second through holes is in a range of 150 μm to 200 μm (Figs. 4, 5A, [0046]; the inner diameter of through holes 21, 22 are 120 μm or more and 190 μm or less).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Gailus’ wiring substrate, as modified by Rubin and Kimishima ‘107, with Kimishima’s through holes in order to provide a core insulating plate, in which a through hole that connects to each other wiring conductors formed on both sides of the core insulating plate is formed, and the through hole is filled with a filling resin, as suggested by Kimishima at [0003].
Regarding claim 12, Gailus in view of Rubin and Kimishima ‘107 discloses the claimed invention as applied to claim 2, above.
Gailus does not disclose the limitations of claim 12.
Kimishima discloses the insulating layer has a thickness in a range of 1.0 mm to 2.0 mm (Figs. 4, 5A, [0063]; the insulating layer 3 has a thickness of 1000 μm or more and 2000 μm or less).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Gailus’ wiring substrate, as modified by Rubin and Kimishima ‘107, with Kimishima’s insulating layer thickness in order to provide a core insulating plate, in which a through hole that connects to each other wiring conductors formed on both sides of the core insulating plate is formed, and the through hole is filled with a filling resin, as suggested by Kimishima at [0003].
Regarding claim 13, Gailus in view of Rubin and Kimishima ‘107 discloses the claimed invention as applied to claim 2, above.
Gailus does not disclose the limitations of claim 13.
Kimishima discloses the plurality of interlayer conductors is formed such that each of the interlayer conductors has a hollow part and includes resin filling the hollow part (Figs. 4, 5A, [0026]; hollow parts 5a penetrate the first interlayer conductors 51, 52 and are filled with resin bodies 6).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Gailus’ wiring substrate, as modified by Rubin and Kimishima ‘107, with Kimishima’s interlayer conductor holes in order to provide a core insulating plate, in which a through hole that connects to each other wiring conductors formed on both sides of the core insulating plate is formed, and the through hole is filled with a filling resin, as suggested by Kimishima at [0003].
Regarding claim 15, Gailus in view of Rubin, Kimishima ‘107 and Kimishima discloses the claimed invention as applied to claim 3, above.
Gailus does not discloses the limitations of claim 15.
Kimishima discloses the insulating layer is formed such that the inner diameter of each of the first through holes is in a range of 160 μm to 220 μm and that the inner diameter of each of the second through holes is in a range of 150 μm to 200 μm (Figs. 4, 5A, [0046]; the inner diameter of through holes 21, 22 are 120 μm or more and 190 μm or less).
Regarding claim 17, Gailus in view of Rubin, Kimishima ‘107 and Kimishima discloses the claimed invention as applied to claim 3, above.
Gailus does not disclose the limitations of claim 17.
Kimishima discloses the insulating layer has a thickness in a range of 1.0 mm to 2.0 mm (Figs. 4, 5A, [0063]; the insulating layer 3 has a thickness of 1000 μm or more and 2000 μm or less).
Regarding claim 18, Gailus in view of Rubin, Kimishima ‘107 and Kimishima discloses the claimed invention as applied to claim 3, above.
Gailus does not disclose the limitations of claim 18.
Kimishima discloses the plurality of interlayer conductors is formed such that each of the interlayer conductors has a hollow part and includes resin filling the hollow part (Figs. 4, 5A, [0026]; hollow parts 5a penetrate the first interlayer conductors 51, 52 and are filled with resin bodies 6).
Regarding claim 19, Gailus in view of Rubin, Kimishima ‘107 and Kimishima discloses the claimed invention as applied to claim 3, above.
Gailus discloses 19. The wiring substrate according to claim 3, wherein the insulating layer has a component mounting region formed such that the second region is overlapping with the component mounting region and that the first region is surrounding the second region (Figs. 8, 14, [0094]-[0096]; the second region is overlapping with the component mounting region and that the first region is surrounding the second region).
Claims 4 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Gailus in view of Rubin and Kimishima.
Regarding claim 4, Gailus in view of Rubin discloses the claimed invention as applied to claim 1, above.
Gailus does not disclose the limitations of claim 4.
Kimishima discloses the insulating layer is formed such that the inner diameter of each of the first through holes is in a range of 160 μm to 220 μm and that the inner diameter of each of the second through holes is in a range of 150 μm to 200 μm (Figs. 4, 5A, [0046]; the inner diameter of through holes 21, 22 are 120 μm or more and 190 μm or less).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Gailus’ wiring substrate, as modified by Rubin, with Kimishima’s through holes in order to provide a core insulating plate, in which a through hole that connects to each other wiring conductors formed on both sides of the core insulating plate is formed, and the through hole is filled with a filling resin, as suggested by Kimishima at [0003].
Regarding claim 6, Gailus in view of Rubin discloses the claimed invention as applied to claim 1, above.
Gailus does not disclose the limitations of claim 6.
Kimishima discloses the insulating layer has a thickness in a range of 1.0 mm to 2.0 mm (Figs. 4, 5A, [0063]; the insulating layer 3 has a thickness of 1000 μm or more and 2000 μm or less).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Gailus’ wiring substrate, as modified by Rubin, with Kimishima’s insulating layer thickness in order to provide a core insulating plate, in which a through hole that connects to each other wiring conductors formed on both sides of the core insulating plate is formed, and the through hole is filled with a filling resin, as suggested by Kimishima at [0003].
Regarding claim 7, Gailus in view of Rubin discloses the claimed invention as applied to claim 1, above.
Gailus does not disclose the limitations of claim 7.
Kimishima discloses the plurality of interlayer conductors is formed such that each of the interlayer conductors has a hollow part and includes resin filling the hollow part (Figs. 4, 5A, [0026]; hollow parts 5a penetrate the first interlayer conductors 51, 52 and are filled with resin bodies 6).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Gailus’ wiring substrate, as modified by Rubin, with Kimishima’s interlayer conductor holes in order to provide a core insulating plate, in which a through hole that connects to each other wiring conductors formed on both sides of the core insulating plate is formed, and the through hole is filled with a filling resin, as suggested by Kimishima at [0003].
Claim 5 is are rejected under 35 U.S.C. 103 as being unpatentable over Gailus in view of Rubin and “Adib” (US 2020/0139677).
Regarding claim 5, Gailus in view of Rubin discloses the claimed invention as applied to claim 1, above.
Gailus does not disclose the limitations of claim 5.
Adib discloses the insulating layer is formed such that a density of the first through holes in the first region is in a range of 0.6 holes/mm2 to 1.2 holes/mm2 and that a density of the second through holes in the second region is in a range of 6 holes/mm2 to 10 holes/mm2 (Fig. 8, [0142], [0153]; the vias 60 have are arranged with a density typically 1 to 20 vias per square millimeter, depending on design and application).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Gailus’ wiring substrate, as modified by Rubin, with Adib’s density in order to provide an insulated layer article having a device modified surface for use in or as, for example, an electrical or an electronic device, as suggested by Adib at [0005].
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Gailus in view of Rubin, Kimishima ‘107 and “Adib” (US 2020/0139677).
Regarding claim 11, Gailus in view of Rubin and Kimishima ‘107 discloses the claimed invention as applied to claim 2, above.
Gailus does not disclose the limitations of claim 11.
Adib discloses the insulating layer is formed such that a density of the first through holes in the first region is in a range of 0.6 holes/mm2 to 1.2 holes/mm2 and that a density of the second through holes in the second region is in a range of 6 holes/mm2 to 10 holes/mm2 (Fig. 8, [0142], [0153]; the vias 60 have are arranged with a density typically 1 to 20 vias per square millimeter, depending on design and application).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Gailus’ wiring substrate, as modified by Rubin and Kimishima ‘107 with Adib’s density in order to provide an insulated layer article having a device modified surface for use in or as, for example, an electrical or an electronic device, as suggested by Adib at [0005].
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Gailus in view of Rubin, Kimishima ‘107, Kimishima and “Adib” (US 2020/0139677).
Regarding claim 16, Gailus in view of Rubin, Kimishima ‘107 and Kimishima discloses the claimed invention as applied to claim 3, respectively above.
Gailus does not disclose the limitations of claims 5, 11 and 16.
Adib discloses the insulating layer is formed such that a density of the first through holes in the first region is in a range of 0.6 holes/mm2 to 1.2 holes/mm2 and that a density of the second through holes in the second region is in a range of 6 holes/mm2 to 10 holes/mm2 (Fig. 8, [0142], [0153]; the vias 60 have are arranged with a density typically 1 to 20 vias per square millimeter, depending on design and application).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Gailus’ wiring substrate, as modified by Rubin, Kimishima ‘107, and Kimishima, with Adib’s density in order to provide an insulated layer article having a device modified surface for use in or as, for example, an electrical or an electronic device, as suggested by Adib at [0005].
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Gailus in view of Rubin, Kimishima and Adib.
Regarding claim 20, Gailus in view of Rubin and Kimishima discloses the claimed invention as applied to claim 4, respectively above.
Gailus does not disclose the limitations of claim 20.
Adib discloses the insulating layer is formed such that a density of the first through holes in the first region is in a range of 0.6 holes/mm2 to 1.2 holes/mm2 and that a density of the second through holes in the second region is in a range of 6 holes/mm2 to 10 holes/mm2 (Fig. 8, [0142], [0153]; the vias 60 have are arranged with a density typically 1 to 20 vias per square millimeter, depending on design and application).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Gailus’ wiring substrate, as modified by Rubin and Kimishima, with Adib’s density in order to provide an insulated layer article having a device modified surface for use in or as, for example, an electrical or an electronic device, as suggested by Adib at [0005].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANLEY TSO whose telephone number is (571)270-0723. The examiner can normally be reached Tu-Thurs 6am-6pm, alt M 6am-2pm.
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/STANLEY TSO/Primary Examiner, Art Unit 2847
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