Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1 – 18 are presented for examination.
Priority
Applicant’s claim for the benefit of a prior-filed application under 3 35 U.S.C. 120 is acknowledged.
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/11/2024 was received. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1 – 18 are rejected on the ground of nonstatutory double patenting over claims 1 – 18 of U.S. Patent No. 12,117,902 since the claims, if allowed, would improperly extend the “right to exclude” already granted in the patent.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows:
Claim 1 – Application 18/882152
Claim 1 – Patent 12,117,902
A method of controlling a semiconductor memory including a word line and a plurality of memory cells connected to the word line, the method comprising:
A memory system comprising: a semiconductor memory including a word line and a plurality of memory cells connected to the word line; and a memory controller configured to write data in the memory cells, wherein the memory controller configured to:
reading data of the memory cells as first data;
read data of the memory cells as first data;
performing error correction on the first data; and
perform error correction on the first data; and
determining whether or not to perform a refresh operation of a block based on a number of error bits of the first data, a first number and a second number, the first number representing a number of bits each of which has different values in a first manner between the first data and first expected data obtained by the error correction on the first data, the second number representing a number of bits each of which has different values in a second manner between the first data and the first expected data, the block having the memory cells.
determine whether or not to perform a refresh operation of a block based on a number of error bits of the first data, a first number and a second number, the first number representing a number of bits each of which has different values in a first manner between the first data and first expected data obtained by the error correction on the first data, the second number representing a number of bits each of which has different values in a second manner between the first data and the first expected data, the block having the memory cells.
One of ordinary skill in the art would clearly recognize independent claim 1, of application 18/882152 is an obvious variation of the claimed subject matter of independent claim 1, of patent 12,117,902. Specifically, both claim 1, of the current application 18/882152, and claim 1, of patent 12,117,902 discloses: “reading data of the memory cells as first data; performing error correction on the first data, determining whether or not to perform a refresh operation of a block based on a number of error bits of the first data”.
One of ordinary skill in the art would recognize the method disclosed by claim 1, of the current application 18/882152, as a direct recitation of the operations performed by the memory system disclosed in claim 1 of Patent 12,117,902. A method performing the operations of a disclosed memory system and a memory system capable of performing a disclosed method would be recognize by one of ordinary skill in the art as obvious variants of each other.
Therefore, one of ordinary skill in the art would recognize the method claim 1, of the current application 18/882152, as performing the operations of the memory system of claim 1, of U.S. Patent 12,117,902, and as such are obvious variants of each other.
Claim 2 – Application 18/882152
Claim 2 – Patent 18/882152
Claim 3 – Application 18/882152
Claim 3 – Patent 18/882152
Claim 4 – Application 18/882152
Claim 4 – Patent 18/882152
Claim 5 – Application 18/882152
Claim 5 – Patent 18/882152
Claim 6 – Application 18/882152
Claim 6 – Patent 18/882152
Claim 7 – Application 18/882152
Claim 7 – Patent 18/882152
Claim 8 – Application 18/882152
Claim 8 – Patent 18/882152
Claim 9 – Application 18/882152
Claim 9 – Patent 18/882152
Claim 10 – Application 18/882152
Claim 10 – Patent 18/882152
Claim 11 – Application 18/882152
Claim 11 – Patent 18/882152
Claim 12 – Application 18/882152
Claim 12 – Patent 18/882152
Claim 13 – Application 18/882152
Claim 13 – Patent 18/882152
Claim 14 – Application 18/882152
Claim 14 – Patent 18/882152
Claim 15 – Application 18/882152
Claim 15 – Patent 18/882152
Claim 16 – Application 18/882152
Claim 16 – Patent 18/882152
Claim 17 – Application 18/882152
Claim 17 – Patent 18/882152
Claim 18 – Application 18/882152
Claim 18 – Patent 18/882152
Claims 1 and 3 – 18 are rejected on the ground of nonstatutory double patenting over claims 1 – 16 of U.S. Patent No. 11,698,834 since the claims, if allowed, would improperly extend the “right to exclude” already granted in the patent.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter.
One of ordinary skill in the art would clearly recognize independent claim 1, of application 18/882152 is an obvious variation of the claimed subject matter of independent claim 1, of patent 11,698,834. Specifically, both claim 1, of the current application 18/882152, and claim 1, of patent 11,698,834 discloses: a method of controlling a semiconductor memory, including a word line and a plurality of memory cells connected to the word line; and, comprising such operations as “read data of the memory cells as first data; perform error correction on the first data”.
One of ordinary skill in the art would recognize the method disclosed by claim 1, of the current application 18/882152, as a broad recitation of the operations performed by the method of controlling a semiconductor memory disclosed in claim 1 of Patent 11,698,834. A method performing the operations of and a method capable of performing a disclosed operations would be recognize by one of ordinary skill in the art as obvious variants of each other.
Therefore, one of ordinary skill in the art would recognize the method of claim 1, of the current application 18/882152, as performing the operations of the method of claim 1, of U.S. Patent 11,698,834, and as such are obvious variants of each other.
Claim 1 – Application 18/882152
Claim 1 – Patent 11,698,834
Claim 3 – Application 18/882152
Claim 1 – Patent 11,698,834
Claim 4 – Application 18/882152
Claim 2 – Patent 11,698,834
Claim 5 – Application 18/882152
Claim 3 – Patent 11,698,834
Claim 6 – Application 18/882152
Claim 4 – Patent 11,698,834
Claim 7 – Application 18/882152
Claim 5 – Patent 11,698,834
Claim 8 – Application 18/882152
Claim 6 – Patent 11,698,834
Claim 9 – Application 18/882152
Claim 7 – Patent 11,698,834
Claim 10 – Application 18/882152
Claim 8 – Patent 11,698,834
Claim 11 – Application 18/882152
Claim 9 – Patent 11,698,834
Claim 12 – Application 18/882152
Claim 10 – Patent 11,698,834
Claim 13 – Application 18/882152
Claim 11 – Patent 11,698,834
Claim 14 – Application 18/882152
Claim 12 – Patent 11,698,834
Claim 15 – Application 18/882152
Claim 13 – Patent 11,698,834
Claim 16 – Application 18/882152
Claim 14 – Patent 11,698,834
Claim 17 – Application 18/882152
Claim 15 – Patent 11,698,834
Claim 18 – Application 18/882152
Claim 16 – Patent 11,698,834
Claims 1 and 3 — 18 are rejected on the ground of nonstatutory double patenting over claims 1 — 16 of U.S. Patent No. 11,334,432 since the claims, if allowed, would improperly extend the “right to exclude” already granted in the patent.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter.
One of ordinary skill in the art would clearly recognize independent claim 1, of application 18/882152 is an obvious variation of the claimed subject matter of independent claim 1, of patent 11,334,432. Specifically, both claim 1, of the current application 18/882152, and claim 1, of patent 11,334,432 discloses: “reading data of the memory cells as first data” and performing error correction.
One of ordinary skill in the art would recognize the method disclosed by claim 1, of the current application 18/882152, as an obvious recitation of the operations performed by the memory system disclosed in claim 1 of Patent 11,334,432. A method performing the operations of a disclosed Memory System and a Memory System capable of performing a disclosed method would be recognize by one of ordinary skill in the art as obvious variants of each other.
Therefore, one of ordinary skill in the art would recognize the method claim 1, of the current application 18/882152, as performing the operations of the apparatus of claim 1, of U.S. Patent 11,334,432, and as such are obvious variants of each other.
Claim 1 – Application 18/882152
Claim 1 – Patent 11,334,432
Claim 3 – Application 18/882152
Claim 1 – Patent 11,334,432
Claim 4 – Application 18/882152
Claim 2 – Patent 11,334,432
Claim 5 – Application 18/882152
Claim 3 – Patent 11,334,432
Claim 6 – Application 18/882152
Claim 4 – Patent 11,334,432
Claim 7 – Application 18/882152
Claim 5 – Patent 11,334,432
Claim 8 – Application 18/882152
Claim 6 – Patent 11,334,432
Claim 9 – Application 18/882152
Claim 7 – Patent 11,334,432
Claim 10 – Application 18/882152
Claim 8 – Patent 11,334,432
Claim 11 – Application 18/882152
Claim 9 – Patent 11,334,432
Claim 12 – Application 18/882152
Claim 10 – Patent 11,334,432
Claim 13 – Application 18/882152
Claim 11 – Patent 11,334,432
Claim 14 – Application 18/882152
Claim 12 – Patent 11,334,432
Claim 15 – Application 18/882152
Claim 13 – Patent 11,334,432
Claim 16 – Application 18/882152
Claim 14 – Patent 11,334,432
Claim 17 – Application 18/882152
Claim 15 – Patent 11,334,432
Claim 18 – Application 18/882152
Claim 16 – Patent 11,334,432
Claims 1 and 3 – 18 are rejected on the ground of nonstatutory double patenting over claims 1 of U.S. Patent No. 10,866,860 since the claims, if allowed, would improperly extend the “right to exclude” already granted in the patent.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter.
One of ordinary skill in the art would clearly recognize independent claim 1, of application 18/882152 is an obvious variation of the claimed subject matter of independent claim 1, of patent 10,866,860. Specifically, both claim 1, of the current application 18/882152, and claim 1, of patent 10,866,860 discloses: “reading data of the memory cells as first data” and performing error correction.
One of ordinary skill in the art would recognize the method disclosed by claim 1, of the current application 18/882152, as an obvious recitation of the operations performed by the memory system disclosed in claim 1 of Patent 10,866,860. A method performing the operations of a disclosed Memory System and a Memory System capable of performing a disclosed method would be recognize by one of ordinary skill in the art as obvious variants of each other.
Therefore, one of ordinary skill in the art would recognize the memory system of claim 1, of the current application 18/882152, as a broader recitation of claim 1, of U.S. Patent 10,866,860, and as such are obvious variants of each other.
Claim 1 – Application 18/882152
Claim 1 – Patent 10,866,860
Claim 3 – Application 18/882152
Claim 1 – Patent 10,866,860
Claim 4 – Application 18/882152
Claim 2 – Patent 10,866,860
Claim 5 – Application 18/882152
Claim 3 – Patent 10,866,860
Claim 6 – Application 18/882152
Claim 4 – Patent 10,866,860
Claim 7 – Application 18/882152
Claim 5 – Patent 10,866,860
Claim 8 – Application 18/882152
Claim 6 – Patent 10,866,860
Claim 9 – Application 18/882152
Claim 7 – Patent 10,866,860
Claim 10 – Application 18/882152
Claim 8 – Patent 10,866,860
Claim 11 – Application 18/882152
Claim 9 – Patent 10,866,860
Claim 12 – Application 18/882152
Claim 10 – Patent 10,866,860
Claim 13 – Application 18/882152
Claim 11 – Patent 10,866,860
Claim 14 – Application 18/882152
Claim 12 – Patent 10,866,860
Claim 15 – Application 18/882152
Claim 13 – Patent 10,866,860
Claim 16 – Application 18/882152
Claim 14 – Patent 10,866,860
Claim 17 – Application 18/882152
Claim 15 – Patent 10,866,860
Claim 18 – Application 18/882152
Claim 16 – Patent 10,866,860
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL F MCMAHON whose telephone number is (571)270-3232. The examiner can normally be reached Monday-Thursday 9am - 5pm EST.
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/Daniel F. McMahon/Primary Examiner, Art Unit 2111