DETAILED ACTION
This action is responsive to the response filed 11 Sep 2024 and the Information Disclosure Statement filed 3 Jan 2025. Claims 1-20 are pending. Claims 1 and 14 are independent. Claims 15-20 have been restricted and withdrawn.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
In the letter dated 8 Jun 2026, the applicant elected claims 1-14 without traverse for examination. Applicant further elected species 2 of figures 7, 8, 10, 12 and 14.
Claims 15-20 have been withdrawn pending further action.
Notice of Foreign Priority Claim
Acknowledgment is made of applicant’s claim for foreign priority. It is noted, however, that applicant has not filed a certified copy of the application KR10-2023-012808 as required by 37 CFR 1.55.
Applicant was notified 12 May 2025 by the USPTO that the priority document could not be retrieved under the exchange program.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3 Jan 2025 is acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Allowable Subject Matter
Claims 2 – 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Rajendra, et al, U.S. Patent Application Publication 2020/0076412 (“Rajendra”) in view of Noguchi, et al, U.S. Patent Application Publication 2022/0215880 (“Noguchi”).
Regarding claim 1, Rajendra teaches:
A pulse signal generator comprising: a delay unit that receives a clock signal, delays the clock signal, and outputs a delay clock signal while adjusting a delay time of the delay clock signal (Rajendra, fig 3, 4, 5, “[0060] Fig 3 shows a block diagram… In general, the duty cycle correction circuit 300 is configured to correct for duty cycle distortion in a pair of input sample clock signals, including a first input sample clock signal SCLKINl and a second input sample clock signal SCLKIN2. [0062] Also, the output sample clock signals SCLKOUT1, SCLKOUT2 are referred to as output signals in that they are the signals that the duty cycle correction circuit 300 outputs in response to performing duty cycle correction.”; a pulse generating circuit 300 to alter an input clock cycle and output two altered clock signals based on a delay controller).
a pulse generation circuit that receives the clock signal and the delay clock signal whose delay time is adjusted…, and logically combines them to generate a pulse signal … (Rajendra, fig 3, 4, 5, “[0066] In the example configuration shown in FIG. 3, the AND/OR logic circuit 302 is configured to generate the first output sample clock signal SCLKOUTl according to OR logic on a first pair of sample clock signals, and the second output clock signal SCLKOUT2 according to AND logic on a second pair of sample clock signals. … The second pair of sample clock signals includes the second input sample clock signal SCLKIN2 and a delayed second input sample clock signal SCLKIN2d.”; a pulse generating circuit 300 that uses a logic AND gate with the input clock SCLKIN2 and the delayed clock SCKLIN2d to produce a shortened pulse).
Rajendra does not explicitly teach depending on Temperature; and … depending on Temperature… having a pulse width that varies depending on Temperature..
Noguchi teaches depending on Temperature; and … depending on Temperature… having a pulse width that varies depending on Temperature. (Noguchi, fig 2, 3A-3C, “[0028] As shown in FIG. 2, the method begins at step 202, where a temperature of the memory cell array 102 is detected by the temperature sensor 134. At step 204, a target write pulse width is determined based on the detected temperature of the memory device, as explained below with reference to FIGS. 3A-3C. [0029] The temperature dependent table 302a provides the target write pulse width 306 according to the temperature 304 of the memory cell array 102.”; a pulse generating device for a memory circuit that alters the pulse width explicitly based on temperature; that the pulses get shorter as the temperature increases).
In view of the teachings of Noguchi it would have been obvious for a person of ordinary skill in the art to apply the teachings of Noguchi to Rajendra before the effective filing date of the claimed invention in order to teach pulse generation. The teachings of Noguchi, in the same or in a similar field of endeavor with Rajendra, can combine Noguchi’s pulse width dependent on temperature and Rajendra’s less explicitly controlled pulse width. The two methods of controlling a pulse width for a clock in a memory cell merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 14, Rajendra, as modified by Noguchi, teaches the pulse signal generator according to claim 1.
Noguchi further teaches wherein the pulse generation circuit includes: an inverter that inverts the delay clock signal and outputs an inverted delay clock signal; and a logical AND circuit that logically ANDs the clock signal and the inverted delay clock signal to output the logical AND. (Noguchi, fig 3, 4, 5, “[0066] In the example configuration shown in FIG. 3, the AND/OR logic circuit 302 is configured to generate the first output sample clock signal SCLKOUTl according to OR logic on a first pair of sample clock signals, and the second output clock signal SCLKOUT2 according to AND logic on a second pair of sample clock signals. … The second pair of sample clock signals includes the second input sample clock signal SCLKIN2 and a delayed second input sample clock signal SCLKIN2d. [0082] As shown in FIG. 6, the NOR logic circuit 602 and the NAND logic circuit 604 are each configured as a push-pull circuit. In general, a push-pull circuit is a circuit that generates an output signal at an output node by pulling up a magnitude ( such as a voltage) of the output signal to an associated high level and by pushing down the magnitude of the output signal to an associated low level.”; a pulse generating circuit 300 that uses a logic AND gate with the input clock SCLKIN2 and the delayed clock SCKLIN2d to produce a shortened pulse; that the SCLKIN2 can be a CLKINb or inverted input; that AND/ OR/ NAND/ NOR gates (of figure 6 can be “obviously combined” under section 103 such that a finite number of inputs (clock signal, inverted clock signal, etc.) with either of the input clock signals with either of the delayed signals to produce a logic out signal).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONALD H.B. BRASWELL whose telephone number is (469)295-9119. The examiner can normally be reached on 7-5 Central Time (Dallas).
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825
Prosecution Insights