DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 18, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 6, and 10 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 10, 11, and 17 of U.S. Patent No. 12,112,831 (“reference patent”) in view of Kwon (US 2002/0176279).
Regarding claim 1: Claim 10 of the reference patent teaches
receiving, by a memory device, a command associated with a region of a non-volatile memory, the command having a command type (“command to access the region”; hence the command is an access type) of a plurality of command types (see “receiving, at a memory device comprising a first non-volatile memory and a second non-volatile memory, a command to access a region of the second non-volatile memory”); and
modifying a value of a counter (see “updating a value of a counter”) based at least in part on the command type corresponding to the command (“based at least in part on receiving the command to access the region”; hence the command is of access type)
Claim 10 of the reference patent does not specifically teach:
the receiving is based at least in part on the memory device transitioning from a second power state to a first power state
Kwon (FIG. 6; [0027,0068-0070]) teaches normal write/read operations being performed based at least in part on a memory device transitioning (in step S60) from a second power state (OFF state) to a first power state (ON state).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kwon into the device and/or method of claim 10 of the reference patent in a manner such that the command would be a read command, among normal access read/write commands, be received based at least in part on the memory device transitioning from a second power state such as an OFF state to a first power state such as an ON state. The motivation to do so would have been to have the memory device be powered ON first to enable it to receive normal operational commands including memory access commands such as a read or write command as exemplified by Kwon.
Regarding claim 6: Claim 11 of the reference patent teaches refraining from accessing the region of the non-volatile memory based at least in part on the value of the counter satisfying a threshold value.
Regarding claim 10: Claim 17 of the reference patent teaches the first power state is a higher power state than the second power state.
Claims 11, 16 and 18-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 10-11 of U.S. Patent No. claim 10 of U.S. Patent No. 12,112,831 (“reference patent”) in view of Athreya et al. (US 2020/0118636) and Kwon (US 2002/0176279).
Regarding claim 11: Claim 10 of the reference patent teaches
one or more memory devices (see “a memory device”); and
receiving, by a memory device, a command associated with a region of a non-volatile memory, the command having a command type (access type); and
modify a value of a counter (updating a value of a counter) based at least in part on the command type corresponding to the command (“command to access the region”).
Claim 10 of the reference patent does not specifically teach:
processing circuitry coupled with the one or more memory devices and configured to control the one or more memory devices; and
the receiving is based at least in part on the memory device transitioning from a second power state to a first power state.
Athreya (FIG. 3A; Host 350 or PROCESSORS 352 within the Host; [0025]) teaches processing circuitry coupled with one or more memory devices and configured to control the one or more memory devices.
Kwon (FIG. 6; [0027,0068-0070]) teaches normal write/read operations being performed based at least in part on a memory device transitioning (in step S60) from a second power state (OFF state) to a first power state (ON state).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Athreya into the device and/or method of claim 10 in a manner such that the one or more memory devices would be coupled to processing circuitry like that of Athreya so that commands or requests may be sent from the processing circuitry to the memory so as to control the memory to read and/or write data. Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kwon into the device and/or method of claim 10 of the reference patent in a manner such that the command would be a read command, among normal access read/write commands, and would be received based at least in part on the memory device transitioning from a second power state such as an OFF state to a first power state such as an ON state. The motivation to do so would have been to have the memory device be powered ON first to enable it to receive normal operational commands including memory access commands such as a read or write command as exemplified by Kwon.
Regarding claim 16: Claim 11 of the reference patent teaches refraining from accessing the region of the non-volatile memory based at least in part on the value of the counter satisfying a threshold value.
Regarding claims 18-19: Claim 10 of the reference patent teaches
receive, by a memory device of the one or more memory devices, a command associated with a region of a non-volatile memory, the command having a command type of a plurality of command type (access type); and
modify a value of a counter (updating a value of a counter) based at least in part on the command type corresponding to the command.
Claim 10 of the reference patent does not specifically teach:
processing circuitry associated with one or more memory devices and configured to cause the apparatus to perform the above; and
the command is based at least in part on the memory device transitioning from a second power state to a first power state.
Athreya (FIG. 3A; Host 350 or PROCESSORS 352 within the Host; [0025]) teaches processing circuitry coupled with one or more memory devices and configured to control the one or more memory devices. Also, Athreya teaches incrementing the value of a counter based at least in part on a command comprising an access command for performing an access operation on a memory region.
Kwon (FIG. 6; [0027,0068-0070]) teaches normal write/read operations being performed based at least in part on a memory device transitioning (in step S60) from a second power state (OFF state) to a first power state (ON state).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Athreya into the device and/or method of claim 10 in a manner such that the one or more memory devices would be coupled to processing circuitry like that of Athreya so that commands or requests may be sent from the processing circuitry to the memory so as to control the memory to read and/or write data, wherein the processing circuity would be configured to cause the apparatus to increment the value of the counter based at least in part on the command comprising an access command for performing an access operation on the region like that taught by Athreya. Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kwon into the device and/or method of claim 10 of the reference patent in a manner such that the command would be a read command, among normal access read/write commands, and would be received based at least in part on the memory device transitioning from a second power state such as an OFF state to a first power state such as an ON state like that taught by Kwon. The motivation to do so would have been to have the memory device be powered ON first to enable it to receive normal operational commands including memory access commands such as a read or write command as exemplified by Kwon.
Claim Objections
Claims 18-20 is objected to because of the following informalities:
Regarding claim 18: The claim claims “wherein the command is based at least in part on the memory device transitioning from a second power state to a first power state”; however, Examiner believes that Applicant intended to claim “wherein receiving the command is based at least in part on the memory device transitioning from a second power state to a first power state”. Please correct.
Claims 19-20 depend on claim 18.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 1, 2, 10, 11, 12, and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Athreya et al. (2020/0118636) in view of Kwon (US 2002/0176279).
Regarding claim 1: Athreya (device in FIG. 3A-B with method of FIG. 6, [0042-0048]) teaches a method, comprising:
receiving, by a memory device (a non-volatile memory device such as 300 in FIG. 3 ; [0042]), a command (a read request is received in 602) associated with a region (a target sub-group such as a sub-block or a page of memory cells; [0020, 0031, 0043]) of a non-volatile memory, the command having a command type (a read type) of a plurality of command types ([0026] discloses a plurality of command types including read, write and erase); and
modifying a value of a counter based at least in part on the command type corresponding to the command (step 604 in FIG. 6).
Athreya does not specifically teach the command being received based at least in part on the memory device transitioning from a second power state to a first power state.
Kwon ([0027,0068-0070]) teaches normal write/read operations being performed based at least in part on a memory device transitioning (in step S60) from a second power state (OFF state) to a first power state (ON state).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kwon into the device and/or method of Athreya in a manner such that the command would be received based at least in part on the memory device transitioning from a second power state such as an OFF state to a first power state such as an ON state. The motivation to do so would have been to have the memory device be powered ON first to enable it to receive normal operational commands including memory access commands such as a read or write command as exemplified by Kwon.
Regarding claim 2: Athreya as modified above teaches the method of claim 1, wherein modifying the value of the counter comprises: incrementing the value of the counter based at least in part on the command comprising an access command for performing an access operation on the region (step 604 in FIG. 6 of Athreya).
Regarding claim 10: Athreya as modified above teaches the method of claim 1, wherein the first power state is a higher power state (a power ON state wherein a supply voltage of VDD is used) than the second power state (either no supply voltage or something less than VDD since the supply voltage has to ramp up to VDD when transitioning to the power ON state; [0068] of Kwon).
Regarding claim 11: Athreya (memory device in FIG. 3A-B with method of FIG. 6, [0042-0048]) a memory system, comprising:
one or more memory devices (a non-volatile memory device such as 300 in FIG. 3; [0042]); and
processing circuitry (Host 350 or processors 352 in the Host in FIG. 3A) coupled with the one or more memory devices and configured to cause the memory system to:
receive, by a memory device (the one or more memory devices; a non-volatile memory device; [0042]), a command (a read request is received in 602) associated with a region (a target sub-group such as a sub-block or a page of memory cells; [0020, 0031, 0043]) of a non-volatile memory, the command having a command type (a read type) of a plurality of command types ([0026] discloses a plurality of command types including read, write and erase); and
modify a value of a counter based at least in part on the command type corresponding to the command (step 604 in FIG. 6).
Athreya does not specifically teach the receiving of the command is based at least in part on the memory device transitioning from a second power state to a first power state
Kwon ([0027,0068-0070]) teaches normal write/read operations being performed based at least in part on a memory device transitioning (in step S60) from a second power state (OFF state) to a first power state (ON state).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kwon into the device and/or method of Athreya in a manner such that the command would be received based at least in part on the memory device transitioning from a second power state such as an OFF state to a first power state such as an ON state. The motivation to do so would have been to have the memory device be powered ON first to enable it to receive normal operational commands including memory access commands such as a read or write command as exemplified by Kwon.
Regarding claim 12: Athreya as modified above teaches the system, wherein to modify the value of the counter, the processing circuitry is configured to cause the memory system to:
increment the value of the counter based at least in part on the command comprising an access command for performing an access operation on the region (step 604 in FIG. 6 of Athreya).
Regarding claim 18: Athreya (memory device in FIG. 3A-B with method of FIG. 6, [0042-0048]) teaches an apparatus, comprising:
processing circuitry (Host 350 or processors 352 in the Host in FIG. 3A) coupled with the one or more memory devices and configured to cause the apparatus to:
receive, by a memory device of the one or more memory devices (the one or more memory devices; a non-volatile memory device; [0042]), a command (a read request is received in 602) associated with a region (a target sub-group such as a sub-block or a page of memory cells; [0020, 0031, 0043]) of a non-volatile memory, the command having a command type (a read type) of a plurality of command types ([0026] discloses a plurality of command types including read, write and erase); and
modify a value of a counter based at least in part on the command type corresponding to the command (step 604 in FIG. 6).
Athreya does not specifically teach the “the command” as in “receiving of the command” is based at least in part on the memory device transitioning from a second power state to a first power state
Kwon ([0027,0068-0070]) teaches normal write/read operations being performed based at least in part on a memory device transitioning (in step S60) from a second power state (OFF state) to a first power state (ON state).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kwon into the device and/or method of Athreya in a manner such that the command would be received based at least in part on the memory device transitioning from a second power state such as an OFF state to a first power state such as an ON state. The motivation to do so would have been to have the memory device be powered ON first to enable it to receive normal operational commands including memory access commands such as a read or write command as exemplified by Kwon.
Regarding claim 19: Athreya as modified above teaches the system, wherein the processing circuitry is configured to cause the apparatus to:
increment the value of the counter based at least in part on the command comprising an access command (a read request) for performing an access operation on the region (step 604 in FIG. 6 of Athreya).
Claim(s) 7-9 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over (2020/0118636) as modified by Kwon (US 2002/0176279) in view of Jeong (2009/0285008) and Lee (2008/0266970).
Regarding claim 7: Athreya as modified by Kwon does not specifically teach the method of claim 1, further comprising:
receiving a second command to transition from the first power state to the second power state; and
storing the value of the counter to a second non-volatile memory based at least in part on receiving the second command.
Jeong (2009/0285008; [0061-0064]) states “The count initializing data is data for setting an initial count value of a write counter 281 and a read counter 282. The count values of the read and counters 281 and 282 may be stored in the cell array 210 or other a non-volatile storage region during a power-off operation.”
Lee (2008/0266970; [0023-0031, 0057-0058, 0064]) teaches storing a count value, upon power-down, from a counter to a non-volatile memory (830 in FIG. 8) that is part of a main memory array (see 260 in 204 in FIG. 2B)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Jeong into the device and/or method of Athreya as modified in a manner such that:
a second command (a power-down or power OFF command) to transition from the first power state to the second power state would be received; and
the value of the counter (a counter in 303 in FIG. 3B and in 315 of FIG. 3A of Athreya) would be stored to a second non-volatile memory (in a portion of the memory 201 in FIG. 3A of Athreya) based at least in part on receiving the second command
The motivation to do so would have been to securely store the count value before power down so that the value would be provided to the counter upon powering ON as disclosed by Jeong.
Regarding claim 8: Athreya (FIG. 6) as modified above teaches the method of claim 7, wherein modifying the value of the counter is based at least in part on accessing the second non-volatile memory (see modification above, wherein the count is saved during power OFF in a portion of the same memory array, whose access is being counted).
Regarding claim 9: Athreya (FIG. 6) as modified above teaches the method of claim 7, wherein the second non-volatile memory comprises a register ([0031] of Lee: a secondary memory array 260 with secondary memory blocks 2651 to 265L) for storing the value of the counter.
Regarding claim 17: Athreya as modified by Kwon does not specifically teach the processing circuitry is further configured to cause the memory system to:
receive a second command to transition from the first power state to the second power state; and
store the value of the counter to a second non-volatile memory based at least in part on receiving the second command.
Jeong (2009/0285008; [0061-0064]) states “The count initializing data is data for setting an initial count value of a write counter 281 and a read counter 282. The count values of the read and counters 281 and 282 may be stored in the cell array 210 or other a non-volatile storage region during a power-off operation.”
Lee (2008/0266970; [0023-0031, 0057-0058, 0064]) teaches storing a count value, upon power-down, from a counter to a non-volatile memory (830 in FIG. 8) that is part of a main memory array (see 260 in 204 in FIG. 2B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Jeong into the device and/or method of Athreya as modified in a manner such that the processing circuitry would be further configured to cause the memory system to:
receive a second command (a power-down or power OFF command) to transition from the first power state to the second power state would; and
store the value of the counter (a counter in 303 in FIG. 3B and in 315 of FIG. 3A of Athreya) to a second non-volatile memory (in a portion of the memory 201 in FIG. 3A of Athreya) based at least in part on receiving the second command
The motivation to do so would have been to securely store the count value before power down so that the value would be provided to the counter upon powering ON as disclosed by Jeong.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY W RADKE whose telephone number is (571)270-1622. The examiner can normally be reached M-F 9-6 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JAY W. RADKE
Primary Examiner
Art Unit 2827
/JAY W. RADKE/Primary Examiner, Art Unit 2827
Prosecution Insights