DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on October 17, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 3, 4, 6, 7, 11, 12, 14, 15, and 17-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 15, 16, 19, 20, 21, 22, 23, and 28 of U.S. Patent No. 12,112,828. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reasons below.
Regarding claim 1: Claim 15 of the reference patent teaches a memory system, comprising:
one or more memory devices (see “a memory device”); and
processing circuitry (see “a controller”, which is inherently a processor since the claim requires the claimed controller to cause actions to happen that require instructions or commands) coupled with the one or more memory devices and configured to cause the memory system to:
receive a first activation command to activate a first set of memory cells in a first bank of a memory device of the one or more memory devices (see “receive a first activation command to activate a first set of memory cells in a first bank of the memory device”);
receive, based at least in part on the first activation command, one or more deselect commands, wherein a quantity of the one or more deselect commands is based at least in part on one or more timing constraints associated with the first activation command (see “receive, based at least in part on the first activation command, a quantity of deselect commands, the quantity of deselect commands based at least in part on one or both of a row activation command delay or a column activation command delay, and based at least in part on one or both of a row address to column address delay or an activation command window”); and
receive, based at least in part on the one or more deselect commands, a second activation command to activate a second set of memory cells in a second bank of the memory device (see “receive, based at least in part on the deselect commands, a second activation command to activate a second set of memory cells in a second bank of the memory device”).
Regarding claim 3: Claim 15 of the reference patent teaches the subject matter of this claim.
Regarding claims 4: Claim 16 of the reference patent teaches the subject matter of this claim.
Regarding claims 6: Claim 21 of the reference patent teaches the subject matter of this claim.
Regarding claims 7: Claim 20 of the reference patent teaches the subject matter of this claim.
Regarding claims 11: Claim 19 of the reference patent teaches the subject matter of this claim.
Regarding claim 12: Claim 22 of the reference patent teaches a host system (a controller and a host device), comprising:
one or more interfaces comprising one or more signal paths (the patent claim inherently requires such paths since commands are transmitted) operable for communications with one or more memory systems (claimed first and second memory banks); and
processing circuitry (see “a controller”, which is inherently a processor since the claim requires the claimed controller to cause actions to happen that require instructions or commands) coupled with the one or more interfaces and configured to cause the host system to:
transmit a first activation command to activate a first set of memory cells in a first bank of a memory device (see” transmit a first activation command to activate a first set of memory cells in a first bank of a memory device”);
transmit, based at least in part on the first activation command, one or more deselect commands, wherein a quantity of the one or more deselect commands is based at least in part on one or more timing constraints associated with the first activation command (see “transmit, based at least in part on the first activation command, a quantity of deselect commands, the quantity of deselect commands based at least in part on one or both of a row activation command delay or a column activation command delay, and based at least in part on one or both of a row address to column address delay or an activation command window”); and
transmit, based at least in part on the one or more deselect commands, a second activation command to activate a second set of memory cells in a second bank of the memory device (see “transmit, based at least in part on the deselect commands, a second activation command to activate a second set of memory cells in a second bank of the memory device”).
Regarding claims 14: Claim 22 of the reference patent teaches the subject matter of this claim.
Regarding claims 15: Claim 23 of the reference patent teaches the subject matter of this claim.
Regarding claims 17: Claim 28 of the reference patent teaches the subject matter of this claim.
Regarding claim 18: Claim 1 of the reference patent teaches a method, comprising:
receiving a first activation command to activate a first set of memory cells in a first bank of a memory device (see “receiving a first activation command to activate a first set of memory cells in a first bank of a memory device”);
receiving, based at least in part on the first activation command, one or more deselect commands, wherein a quantity of the one or more deselect commands is based at least in part on one or more timing constraints associated with the first activation command (see “receiving, based at least in part on the first activation command, a quantity of deselect commands, the quantity of deselect commands based at least in part on one or both of a row activation command delay or a column activation command delay, and based at least in part on one or both of a row address to column address delay or an activation command window”); and
receiving, based at least in part on the one or more deselect commands, a second activation command to activate a second set of memory cells in a second bank of the memory device (see “receiving, based at least in part on the deselect commands, a second activation command to activate a second set of memory cells in a second bank of the memory device”).
Regarding claims 19: Claim 3 of the reference patent teaches the subject matter of this claim (the four banks may be considered to be one bank group).
Regarding claims 20: Claim 2 of the reference patent teaches the subject matter of this claim (the four banks may be considered to be one bank group).
Allowable Subject Matter
Claims 2, 5, 8-10, 13, and 16 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY W RADKE whose telephone number is (571)270-1622. The examiner can normally be reached M-F 9-6 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JAY W. RADKE
Primary Examiner
Art Unit 2827
/JAY W. RADKE/Primary Examiner, Art Unit 2827