DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21-23, 28, 31, 33-39, and 45-46 is/are rejected under 35 U.S.C. 103 as being unpatentable over MIYATA (US 20100187640) in view of NAKAO (US 20200185517).
Regarding claim 21, MIYATA discloses a semiconductor device comprising:
a semiconductor layer (substrate SB, see fig 3-4 and 9, para 65) that has a main surface (the top surface of SB, see fig 3), and that has an active region (region 20, see fig 3, para 52) and a non-active region provided in a region outside the active region (the region of the device outside 20, to the right in figs 3 and 9, see para 52);
a switching element (the transistor comprising source 15, channel layer 4, drain 1 and gate 13, see fig 3, para 65) that is formed in the active region of the semiconductor layer, and that has a gate electrode (fig 3-4 and 9, 13, para 66), a source region (source region 15, see fig 3, para 67), and a drain region (fig 3, 1, para 65);
a first electrode (electrode 18 connected to the gate electrode, see fig 3, para 74) that is arranged on the main surface at the non-active region, and that is electrically connected to the gate electrode of the switching element (see para 75);
a first insulating layer (fig 3-4 and 9, 16, para 71) that has contact holes at the active region (the holes in 16 through which 17 contacts SB, see fig 3 and 9);
a second electrode (fig 3-4 and 9, 17, para 52) that is arranged on the main surface via the first insulating layer at an interval from the first electrode at the active region as viewed in plan (17 and 18 are spaced from each other, see fig 3-4), and that is electrically connected to the source region of the switching element via the contact hole (17 is connected to SB through a holes in 16, see fig 3);
a second insulating layer (fig 3 and 9, 23, para 72) that is arranged on the second electrode;
a first terminal electrode (fig 3-4 and 9, 28, para 59) that has a portion overlapping the first electrode and a portion overlapping the second electrode as viewed in plan (28 overlaps with 18 and 17 along a vertical direction, as shown in figs 3-4), that is electrically connected to the first electrode (28 is connected to 18 directly, see fig 3), and that is electrically isolated from the second electrode with the second insulating layer (insulator 23 is between 17 and 28, see fig 3); and
a second terminal electrode (electrode 27, see fig 3-4 and 9, para 58) that has a portion overlapping the second electrode as viewed in plan (27 overlaps with 17 along a vertical direction, see fig 2-3), and that is electrically connected to the second electrode (17 and 27 are directly connected, see fig 3);
wherein the first terminal electrode has a side surface that is arranged at an upper side to the second electrode so as to face the second electrode across the second insulating layer (the bottom side surface of 28 that faces 17, see fig 3-4),
the second terminal electrode has a side surface that is arranged at an upper side to the second electrode so as to face the second electrode across the second insulating layer (the bottom surface of 27 that faces 17, see fig 3), and that forms a gap exposing the second insulating layer between the side surface of the first terminal electrode and the side surface of the second terminal electrode (the gap between 28 and 27 in which the second insulator 23 is exposed to 25, see fig 3 and 9),
the semiconductor device further comprising a third insulating layer that covers the second insulating layer inside the gap and faces the second electrode across the second insulating layer (fig 3 and 9, 25, para 78),
the second insulating layer covers the first electrode (second insulating layer 23 at least partially covers top and side surfaces of the first electrode 18, see fig 3),
the first terminal electrode has a portion that faces the first electrode across the second insulating layer (the first terminal electrode 28 has a portion of the bottom surface of 28c that faces the top surface of the first electrode 18 with 23 between them, see fig 3), and
the second terminal electrode has a portion that faces the first electrode across the second insulating layer (the second terminal electrode 27 has a portion of the bottom-right surface of 27 that faces the side surface of the first electrode 18 with 23 between them, see fig 3).
MIYATA fails to explicitly disclose a device comprising a second electrode that is arranged on the main surface via the first insulating layer at an interval from the first electrode at the active region as viewed in plan, that is arranged in such a manner as to surround a periphery of the first electrode as viewed in plan and that is electrically connected to the source region of the switching element via the contact hole.
NAKAO teaches a device comprising a second electrode (source electrode 80 and 81, see fig 3, para 50) that is arranged on the main surface via the first insulating layer (80 and 81 are on the top surface of the wafer 20 with insulator 55 between them, see fig 5, para 46 and 49) at an interval from the first electrode at the active region as viewed in plan (the source electrode 80 and 81 is separated from the gate electrode 83 and 82 in plan view, see fig 3, para 50), that is arranged in such a manner as to surround a periphery of the first electrode as viewed in plan (80 and 81 surround 82 and 83 in plan, see fig 3) and that is electrically connected to the source region of the switching element via the contact hole (80 is connected to the source region 40 by means of holes in 55, see fig 4, para 39).
MIYATA and NAKAO are analogous art because they both are directed towards semiconductor devices with electrode pads and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of MIYATA with the specific source electrode geometry of NAKAO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of MIYATA with the specific source electrode geometry of NAKAO in order to reduce gate oxide breakdown (see NAKAO para 116).
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Figure I: MIYATA figure 3 with added annotations.
Regarding claim 22, MIYATA and NAKAO disclose the semiconductor device according to Claim 21.
MIYATA further discloses a device, further comprising:
a bonding wire that is bonded to the first terminal electrode (the device can have 28 be connected by a bonding wire, see fig 9, para 134);
wherein the first terminal electrode includes:
a connecting portion (the portion 28w of 28 that connects to 18 via a hole in 23, see fig 9, para 59) that is formed in a through hole formed in the second insulating layer and connected to the first electrode; and
a wide portion that extends to an outside from the connecting portion (the gate pad portion 28p, see fig 9, para 59); and
wherein the bonding wire is bonded to a region that does not overlap the connecting portion as viewed in plan (the portion of 28 under 48 does not overlap with the portion over 18, see fig 9).
Regarding claim 23, MIYATA and NAKAO disclose the semiconductor device according to claim 22.
MIYATA further discloses a device wherein the connecting portion and the wide portion are formed of a same conductive material (28p and 28w both made of 28, see fig 9).
Regarding claim 28, MIYATA and NAKAO disclose the semiconductor device according to claim 21.
MIYATA fails to explicitly disclose a device wherein the semiconductor layer includes SiC.
NAKAO teaches a device wherein the semiconductor layer includes SiC (the device can be a SiC device, see para 33 and 36).
MIYATA and NAKAO are analogous art because they both are directed towards semiconductor devices with electrode pads and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of MIYATA with the specific source electrode geometry of NAKAO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of MIYATA with the specific source electrode geometry of NAKAO in order to reduce gate oxide breakdown (see NAKAO para 116).
Regarding claim 31, MIYATA and NAKAO disclose the semiconductor device according to claim 28.
MIYATA further discloses a device wherein the first electrode includes:
an electricity receiving portion (fig 3, 28c, para 59) that is arranged so as to overlap the first terminal electrode as viewed in plan, and that is electrically connected to the first terminal electrode (28c overlaps and is connected with 18, see fig 3);
an electricity supplying portion that extends along one direction as viewed in plan (the gate pad portion 28p extends in the vertical direction in fig 4, see fig 3, para 59); and
a connecting portion that connects the electricity receiving portion and the electricity supplying portion, and that extends along a direction orthogonal to the one direction (28w connects 28p and 28c and extends in the horizontal direction in fig 2B, see fig 3-4, para 59).
Regarding claim 33, MIYATA and NAKAO disclose the semiconductor device according to Claim 28.
MIYATA further discloses a device, further comprising:
a metal plate (metal electrode 37 on 27, see fig 3, para 79) that is electrically connected to the second terminal electrode; and
a bonding material (the Au layer of 24, see fig 3, para 79) that is interposed between the second terminal electrode and the metal plate;
wherein a first plating layer is formed on an upper surface of the second terminal electrode (the Ni layer of 24, see fig 3, para 79), and
the first plating layer and the metal plate are bonded with the bonding material (see fig 3).
Regarding claim 34, MIYATA and NAKAO disclose the semiconductor device according to claim 33.
MIYATA further discloses a device wherein the first plating layer includes a metal layer including nickel as a main component (the Ni layer of 24 is made of Ni, see fig 3, para 79).
Regarding claim 35, MIYATA and NAKAO disclose the semiconductor device according to claim 34.
MIYATA further discloses a device wherein a second plating layer is formed on an upper surface of the first terminal electrode (a portion of 24 is also connected to 28, see fig 3).
Regarding claim 36, MIYATA discloses a semiconductor device comprising:
a semiconductor layer (substrate SB, see fig 3-4 and 9, para 65) that has a main surface (the top surface of SB, see fig 3), and that has an active region (region 20, see fig 3, para 52) and a non-active region provided in a region outside the active region (the region of the device outside 20, to the right in figs 3 and 9, see para 52);
a switching element (the transistor comprising source 15, channel layer 4, drain 1 and gate 13, see fig 3, para 65) that is formed in the active region of the semiconductor layer, and that has a gate electrode (fig 3-4 and 9, 13, para 66), a source region (source region 15, see fig 3, para 67), and a drain region (fig 3, 1, para 65);
a first electrode (electrode 18 connected to the gate electrode, see fig 3, para 74) that is arranged on the main surface at the non-active region, and that is electrically connected to the gate electrode of the switching element (see para 75);
a first insulating layer (fig 3-4 and 9, 16, para 71) that has contact holes at the active region (the holes in 16 through which 17 contacts SB, see fig 3 and 9);
a second electrode (fig 3-4 and 9, 17, para 52) that is arranged on the main surface via the first insulating layer at an interval from the first electrode at the active region as viewed in plan (17 and 18 are spaced from each other, see fig 3-4), and that is electrically connected to the source region of the switching element via the contact hole (17 is connected to SB through a holes in 16, see fig 3);
a second insulating layer (fig 3 and 9, 23, para 72) that is arranged on the second electrode;
a first terminal electrode (fig 3-4 and 9, 28, para 59) that has a portion overlapping the first electrode and a portion overlapping the second electrode as viewed in plan (28 overlaps with 18 and 17 along a vertical direction, as shown in figs 3-4), that is electrically connected to the first electrode (28 is connected to 18 directly, see fig 3), and that is electrically isolated from the second electrode with the second insulating layer (insulator 23 is between 17 and 28, see fig 3); and
a second terminal electrode (electrode 27, see fig 3-4 and 9, para 58) that has a portion overlapping the second electrode as viewed in plan (27 overlaps with 17 along a vertical direction, see fig 2-3), and that is electrically connected to the second electrode (17 and 27 are directly connected, see fig 3);
wherein the first terminal electrode has a side surface that is arranged at an upper side to the second electrode so as to face the second electrode across the second insulating layer (the bottom side surface of 28 that faces 17, see fig 3-4),
the second terminal electrode has a side surface that is arranged at an upper side to the second electrode so as to face the second electrode across the second insulating layer (the bottom surface of 27 that faces 17, see fig 3), and that forms a gap exposing the second insulating layer between the side surface of the first terminal electrode and the side surface of the second terminal electrode (the gap between 28 and 27 in which the second insulator 23 is exposed to 25, see fig 3 and 9), and
the semiconductor device further comprising a third insulating layer that covers the second insulating layer inside the gap and faces the second electrode across the second insulating layer (fig 3 and 9, 25, para 78),
the semiconductor device further comprising a bonding wire bonded to the first terminal electrode is further provided (the device can have 28 be connected by a bonding wire, see fig 9, para 134),
the first terminal electrode includes a connecting portion (the portion 28w of 28 that connects to 18 via a hole in 23, see fig 9, para 59) that is formed in a through hole formed in the second insulating layer and connected to the first electrode, and
a wide portion (the gate pad portion 28p, see fig 9, para 59) that extends to an outside from the connecting portion,
the bonding wire is bonded to a region that does not overlap the connecting portion as viewed in plan (the portion of 28 under 48 does not overlap with the portion over 18, see fig 9),
the second insulating layer covers the first electrode (second insulating layer 23 at least partially covers top and side surfaces of the first electrode 18, see fig 3),
the first terminal electrode has a portion that faces the first electrode across the second insulating layer (the first terminal electrode 28 has a portion of the bottom surface of 28c that faces the top surface of the first electrode 18 with 23 between them, see fig 3), and
the second terminal electrode has a portion that faces the first electrode across the second insulating layer (the second terminal electrode 27 has a portion of the bottom-right surface of 27 that faces the side surface of the first electrode 18 with 23 between them, see fig 3).
MIYATA fails to explicitly disclose a device comprising a second electrode that is arranged on the main surface via the first insulating layer at an interval from the first electrode at the active region as viewed in plan, that is arranged in such a manner as to surround a periphery of the first electrode as viewed in plan and that is electrically connected to the source region of the switching element via the contact hole; and
the semiconductor layer includes SiC.
NAKAO teaches a device comprising a second electrode (source electrode 80 and 81, see fig 3, para 50) that is arranged on the main surface via the first insulating layer (80 and 81 are on the top surface of the wafer 20 with insulator 55 between them, see fig 5, para 46 and 49) at an interval from the first electrode at the active region as viewed in plan (the source electrode 80 and 81 is separated from the gate electrode 83 and 82 in plan view, see fig 3, para 50), that is arranged in such a manner as to surround a periphery of the first electrode as viewed in plan (80 and 81 surround 82 and 83 in plan, see fig 3) and that is electrically connected to the source region of the switching element via the contact hole (80 is connected to the source region 40 by means of holes in 55, see fig 4, para 39); and
the semiconductor layer includes SiC (the device can be a SiC device, see para 33).
MIYATA and NAKAO are analogous art because they both are directed towards semiconductor devices with electrode pads and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of MIYATA with the specific source electrode geometry of NAKAO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of MIYATA with the specific source electrode geometry of NAKAO in order to reduce gate oxide breakdown (see NAKAO para 116).
Regarding claim 37, MIYATA and NAKAO disclose the semiconductor device according to Claim 36.
MIYATA further discloses a device, further comprising:
a metal plate (metal electrode 37 on 27, see fig 3, para 79) that is electrically connected to the second terminal electrode; and
a bonding material (the Au layer of 24, see fig 3, para 79) that is interposed between the second terminal electrode and the metal plate;
wherein a first plating layer is formed on an upper surface of the second terminal electrode (the Ni layer of 24, see fig 3, para 79), and
the first plating layer and the metal plate are bonded with the bonding material (see fig 3).
Regarding claim 38, MIYATA and NAKAO disclose the semiconductor device according to claim 37.
MIYATA further discloses a device wherein the first plating layer includes a metal layer including nickel as a main component (the Ni layer of 24 is made of Ni, see fig 3, para 79).
Regarding claim 39, MIYATA and NAKAO disclose the semiconductor device according to claim 38.
MIYATA further discloses a device wherein a second plating layer is formed on an upper surface of the first terminal electrode (a portion of 24 is also connected to 28, see fig 3)., and
the bonding wire is bonded to the second plating layer (a bonding wire can also be formed on the source electrode, see para 5).
Regarding claim 41, MIYATA and NAKAO disclose the semiconductor device according to Claim 21.
MIYATA further discloses a device, wherein the second terminal electrode is arranged such as to surround a periphery of the first terminal electrode as viewed in plan (27 completely surrounds the periphery of 28p since going outwards from any direction from 28p will hit 27; additionally 27 at least partially surrounds the periphery of every portion of 28, see fig 4).
Regarding claim 42, MIYATA and NAKAO disclose the semiconductor device according to Claim 21.
MIYATA further discloses a device, wherein the second terminal electrode is formed larger in an area than the first terminal electrode as viewed in plan (an area of MIYATA can be defined such that, in that area, 27 is larger than 28, see fig 2B).
Regarding claim 45, MIYATA and NAKAO disclose the semiconductor device according to Claim 36.
MIYATA further discloses a device, wherein the second terminal electrode is arranged such as to surround a periphery of the first terminal electrode as viewed in plan (27 completely surrounds the periphery of 28p since going outwards from any direction from 28p will hit 27; additionally 27 at least partially surrounds the periphery of every portion of 28, see fig 4).
Regarding claim 46, MIYATA and NAKAO disclose the semiconductor device according to Claim 36.
MIYATA further discloses a device, wherein the second terminal electrode is formed larger in an area than the first terminal electrode as viewed in plan (an area of MIYATA can be defined such that, in that area, 27 is larger than 28, see fig 2B).
Claim(s) 24, 44 and 48 is/are rejected under 35 U.S.C. 103 as being unpatentable over MIYATA (US 20100187640) in view of NAKAO (US 20200185517) and further in view of YAGI (US 20140001539).
Regarding claim 24, MIYATA and NAKAO disclose the semiconductor device according to claim 22.
MIYATA and NAKAO fail to explicitly disclose a device wherein the first terminal electrode is recessed toward the first electrode at a portion overlapping the connecting portion.
YAGI teaches a device wherein the first terminal electrode is recessed toward the first electrode at a portion overlapping the connecting portion (terminal electrode GM is recessed above gate contact 82, see fig 4, para 37).
MIYATA, NAKAO and YAGI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of MIYATA and NAKAO with the electrode shape of YAGI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of MIYATA and NAKAO with the electrode shape of YAGI in order to avoid an increase in on-resistance (see YAGI para 17).
Regarding claim 44, MIYATA and NAKAO disclose the semiconductor device according to Claim 21.
MIYATA and NAKAO fail to explicitly disclose a device, wherein the third insulating layer covers an entire circumference of an outer peripheral portion of the semiconductor layer.
YAGI teaches a device wherein the third insulating layer covers an entire circumference of an outer peripheral portion of the semiconductor layer (insulator 25 covers a top surface of an outer portion of 2, see fig 1-4, para 75).
MIYATA, NAKAO and YAGI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of MIYATA and NAKAO with the electrode shape of YAGI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of MIYATA and NAKAO with the electrode shape of YAGI in order to avoid an increase in on-resistance (see YAGI para 17).
Regarding claim 48, MIYATA and NAKAO disclose the semiconductor device according to Claim 36.
MIYATA and NAKAO fail to explicitly disclose a device, wherein the third insulating layer covers an entire circumference of an outer peripheral portion of the semiconductor layer.
YAGI teaches a device, wherein the third insulating layer covers an entire circumference of an outer peripheral portion of the semiconductor layer (insulator 25 covers a top surface of an outer portion of 2, see fig 1-4, para 75).
MIYATA, NAKAO and YAGI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of MIYATA and NAKAO with the electrode shape of YAGI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of MIYATA and NAKAO with the electrode shape of YAGI in order to avoid an increase in on-resistance (see YAGI para 17).
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over MIYATA (US 20100187640) in view of NAKAO (US 20200185517) and further in view of NOGUCHI (US 6075282).
Regarding claim 24, MIYATA and NAKAO disclose the semiconductor device according to claim 22.
MIYATA and NAKAO fail to explicitly disclose a device wherein the first terminal electrode has an area of not less than 640000 um2 and not more than 1000000 um2.
NOGUCHI teaches a device wherein the first terminal electrode has an area of not less than 640000 um2 and not more than 1000000 um2 (the gate electrode can have an area of 100 by 100 square microns, see paragraph 19).
MIYATA, NAKAO and NOGUCHI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of MIYATA and NAKAO with the electrode area of NOGUCHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of MIYATA and NAKAO with the electrode area of NOGUCHI in order to avoid damage to the device (see NOGUCHI para 20).
Claim(s) 26-27 and 40 is/are rejected under 35 U.S.C. 103 as being unpatentable over MIYATA (US 20100187640) in view of NAKAO (US 20200185517) and further in view of FUKUI (US 20190333986).
Regarding claim 26, MIYATA and NAKAO disclose the semiconductor device according to Claim 22.
MIYATA and NAKAO fail to explicitly disclose a device, further comprising: an end insulating layer that covers an outer peripheral portion of the semiconductor layer;
wherein the first insulating layer covers the outer peripheral portion of the semiconductor layer,
the end insulating layer covers the outer peripheral portion of the semiconductor layer via the first insulating layer, and
the third insulating layer covers the outer peripheral portion of the semiconductor layer via the first insulating layer and the end insulating layer.
FUKUI teaches a device, further comprising: an end insulating layer that covers an outer peripheral portion of the semiconductor layer (insulator layer 7 covers outer portions of 3, see fig 3, para 58 and 64);
wherein the first insulating layer covers the outer peripheral portion of the semiconductor layer (first insulating film 9a covers outer portions of 3, see fig 3, para 74),
the end insulating layer covers the outer peripheral portion of the semiconductor layer via the first insulating layer (7 covers the outer portions of 3 with 9a in the middle, see fig 3, para 58), and
the third insulating layer covers the outer peripheral portion of the semiconductor layer via the first insulating layer and the end insulating layer (third insulating layer 21 covers outer portions of 3 via 9a and 7, see fig 3, para 99).
MIYATA, NAKAO and FUKUI are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of MIYATA and NAKAO with the insulating layers of FUKUI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of MIYATA and NAKAO with the insulating layers of FUKUI in order to improve a short-circuit tolerance of the device (see FUKUI para 107).
Regarding claim 27, MIYATA and NAKAO disclose the semiconductor device according to claim 26.
MIYATA and NAKAO fail to explicitly disclose a device wherein the end insulating layer is formed of a same insulating material as the second insulating layer.
FUKUI teaches a device wherein the end insulating layer is formed of a same insulating material as the second insulating layer (7 and 9 can both be SiO, see fig 3, para 91 and 70).
MIYATA, NAKAO and FUKUI are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of MIYATA and NAKAO with the insulating layers of FUKUI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of MIYATA and NAKAO with the insulating layers of FUKUI in order to improve a short-circuit tolerance of the device (see FUKUI para 107).
Regarding claim 40, MIYATA and NAKAO disclose the semiconductor device according to Claim 36.
MIYATA and NAKAO fail to explicitly disclose a device, further comprising:
an end insulating layer that covers an outer peripheral portion of the semiconductor layer;
wherein the first insulating layer covers the outer peripheral portion of the semiconductor layer,
the end insulating layer covers the outer peripheral portion of the semiconductor layer via the first insulating layer, and
the third insulating layer covers the outer peripheral portion of the semiconductor layer via the first insulating layer and the end insulating layer.
FUKUI teaches a device, further comprising:
an end insulating layer that covers an outer peripheral portion of the semiconductor layer (insulator layer 7 covers outer portions of 3, see fig 3, para 58 and 64);
wherein the first insulating layer covers the outer peripheral portion of the semiconductor layer (first insulating film 9a covers outer portions of 3, see fig 3, para 74),
the end insulating layer covers the outer peripheral portion of the semiconductor layer via the first insulating layer (7 covers the outer portions of 3 with 9a in the middle, see fig 3, para 58), and
the third insulating layer covers the outer peripheral portion of the semiconductor layer via the first insulating layer and the end insulating layer (third insulating layer 21 covers outer portions of 3 via 9a and 7, see fig 3, para 99).
MIYATA, NAKAO and FUKUI are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of MIYATA and NAKAO with the insulating layers of FUKUI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of MIYATA and NAKAO with the insulating layers of FUKUI in order to improve a short-circuit tolerance of the device (see FUKUI para 107).
Claim(s) 29-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over MIYATA (US 20100187640) in view of NAKAO (US 20200185517) and further in view of YOSHIMOCHI (US 201120326207).
Regarding claim 29, MIYATA and NAKAO disclose the semiconductor device according to claim 28.
MIYATA and NAKAO fail to explicitly disclose a device wherein
the second electrode has a first portion that is embedded in the contact hole of the first insulating layer and a second portion that is formed on the first insulating layer,
the first portion includes tungsten or tungsten alloy, and
the second portion includes aluminum or aluminum alloy.
YOSHIMOCHI teaches a device wherein
the second electrode has a first portion that is embedded in the contact hole of the first insulating layer (electrode 53 is in holes in insulator 50, see fig 2, para 128 and 130) and a second portion (the portion 15 and 16 which is above 50, see fig 2, para 102) that is formed on the first insulating layer,
the first portion includes tungsten or tungsten alloy (53 can be tungsten, see fig 2, para 130), and
the second portion includes aluminum or aluminum alloy (15 is a part of 4, which can be AlCu, see fig 2, para 150).
MIYATA, NAKAO and YOSHIMOCHI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of MIYATA and NAKAO with the electrode materials of YOSHIMOCHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of MIYATA and NAKAO with the electrode materials of YOSHIMOCHI in order to improve the device characteristics (see YOSHIMOCHI para 161).
Regarding claim 30, MIYATA and NAKAO disclose the semiconductor device according to claim 29.
MIYATA and NAKAO fail to explicitly disclose a device wherein the first portion is formed via a barrier film made of titanium or titanium nitride.
YOSHIMOCHI teaches a device wherein the first portion is formed via a barrier film made of titanium or titanium nitride (Ti or TiN barrier layers can be formed in 51, see fig 2, para 149).
MIYAT, NAKAO A and YOSHIMOCHI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of MIYATA and NAKAO with the electrode materials of YOSHIMOCHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of MIYATA and NAKAO with the electrode materials of YOSHIMOCHI in order to improve the device characteristics (see YOSHIMOCHI para 161).
Claim(s) 32, 43 and 47 is/are rejected under 35 U.S.C. 103 as being unpatentable over MIYATA (US 20100187640) in view of NAKAO (US 20200185517) and further in view of YOSHIMURA (US 20190252542).
Regarding claim 32, MIYATA and NAKAO disclose the semiconductor device according to Claim 31.
MIYATA and NAKAO fail to explicitly disclose a device, further comprising:
a gate finger portion that is connected to the gate electrode of the switching element, and that has a portion overlapping the electricity supplying portion;
wherein the electricity supplying portion is electrically connected to the gate finger portion via a through hole provided in the first insulating layer.
YOSHIMURA teaches a device, further comprising:
a gate finger portion that is connected to the gate electrode of the switching element (the portion of gate electrode 106 that extends out of trench 104, see fig 3, para 21), and that has a portion overlapping the electricity supplying portion (106 overlaps with a part of 114b that does not overlap with 114a, see fig 3, para 26 and 21);
wherein the electricity supplying portion is electrically connected to the gate finger portion via a through hole provided in the first insulating layer (all of 114b is connected to 106 by a through hole in 116, see fig 3).
MIYATA, NAKAO and YOSHIMURA are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of MIYATA with the through hole via geometry of YOSHIMURA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of MIYATA and NAKAO with the through hole via geometry of YOSHIMURA in order to make a device wherein element region can accordingly be expanded even if the bidirectional diode is formed in the element region (see YOSHIMURA para 8).
Regarding claim 43, MIYATA and NAKAO disclose the semiconductor device according to Claim 21.
MIYATA and NAKAO fails to explicitly disclose a device, wherein the third insulating layer covers the gap formed between the first terminal electrode and the second terminal electrode in a rectangular annular shape as viewed in plan.
YOSHIMURA teaches a device, wherein the third insulating layer covers the gap formed between the first terminal electrode and the second terminal electrode in a rectangular annular shape as viewed in plan (insulator 115 covers the gap between first terminal electrode 114b and second terminal electrode 112b and surrounds 112b (SS) in a rectangular ring in plan view, see fig 1-2, para 33).
MIYATA, NAKAO and YOSHIMURA are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of MIYATA and NAKAO with the through hole via geometry of YOSHIMURA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of MIYATA and NAKAO with the through hole via geometry of YOSHIMURA in order to make a device wherein element region can accordingly be expanded even if the bidirectional diode is formed in the element region (see YOSHIMURA para 8).
Regarding claim 47, MIYATA and NAKAO disclose the semiconductor device according to Claim 36.
MIYATA and NAKAO fail to explicitly disclose a device, wherein the third insulating layer covers the gap formed between the first terminal electrode and the second terminal electrode in a rectangular annular shape as viewed in plan.
YOSHIMURA teaches a device, wherein the third insulating layer covers the gap formed between the first terminal electrode and the second terminal electrode in a rectangular annular shape as viewed in plan (insulator 115 covers the gap between first terminal electrode 114b and second terminal electrode 112b and surrounds 112b (SS) in a rectangular ring in plan view, see fig 1-2, para 33).
MIYATA, NAKAO and YOSHIMURA are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of MIYATA and NAKAO with the through hole via geometry of YOSHIMURA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of MIYATA and NAKAO with the through hole via geometry of YOSHIMURA in order to make a device wherein element region can accordingly be expanded even if the bidirectional diode is formed in the element region (see YOSHIMURA para 8).
Claim(s) 49-50 and 54-55 is/are rejected under 35 U.S.C. 103 as being unpatentable over MIYATA (US 20100187640) in view of NAKAO (US 20200185517) and further in view of SCHWETLICK (US 20160351668).
Regarding claim 49, MIYATA and NAKAO disclose the semiconductor device according to claim 21.
MIYATA further discloses a device,
wherein the first insulating layer is arranged between the semiconductor layer and the first electrode, and between the semiconductor layer and the second electrode (the first insulating layer 16 is between SB and first electrode 18, and between SB and second electrode 17, see fig 3),
the second electrode has a portion that is electrically connected to the source region of the switching element via the contact hole (second electrode 17 is connected to source region 15 by holes in 16, see fig 3, para 67).
MIYATA and NAKAO fail to explicitly disclose a device wherein the portion of the second electrode embedded in the contact hole includes tungsten.
SCHWETLICK teaches a device wherein the portion of the second electrode embedded in the contact hole includes tungsten (310 can be Tungsten, see fig 4, para 74).
MIYATA, NAKAO and SCHWETLICK are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of MIYATA with the material of SCHWETLICK because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of MIYATA and NAKAO with the material of SCHWETLICK in order to reduce the on-state resistance (see SCHWETLICK para 59).
Regarding claim 50, MIYATA and NAKAO disclose the semiconductor device according to claim 21.
MIYATA and NAKAO fails to explicitly disclose a device, further comprising:
a gate finger portion that is arranged below the first insulating layer and that is electrically connected to the gate electrode of the switching element; and
wherein the first insulating layer has a through hole that exposes the gate finger portion,
the first electrode has a portion that is electrically connected to the gate finger portion via the through hole, and
the portion of the first electrode embedded in the through hole includes tungsten.
SCHWETLICK teaches a device, further comprising:
a gate finger portion (fig 4, 165a, para 67) that is arranged below the first insulating layer (165a is below 210, see fig 4, para 71) and that is electrically connected to the gate electrode of the switching element (165a is connected to gate electrode 165b, see fig 4, para 64); and
wherein the first insulating layer has a through hole that exposes the gate finger portion (the through hole in 210 in which 315b is formed, see fig 4B),
the first electrode has a portion that is electrically connected to the gate finger portion via the through hole (first electrode 310 has a portion 315b which connects to 165a, see fig 4B, para 74), and
the portion of the first electrode embedded in the through hole includes tungsten (310 can be Tungsten, see fig 4, para 74).
MIYATA, NAKAO and SCHWETLICK are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of MIYATA and NAKAO with the material of SCHWETLICK because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of MIYATA and NAKAO with the material of SCHWETLICK in order to reduce the on-state resistance (see SCHWETLICK para 59).
Regarding claim 54, MIYATA and NAKAO disclose the semiconductor device according to claim 36.
MIYATA further discloses a device,
wherein the first insulating layer is arranged between the semiconductor layer and the first electrode, and between the semiconductor layer and the second electrode (16 is located between the semiconductor layer SB and 17 and between SB and 18, see fig 3),
the second electrode has a portion that is electrically connected to the source region of the switching element via the contact hole (17 is connected to source 15 by holes in 16, see fig 3).
MIYATA and NAKAO fail to explicitly disclose a device wherein the portion of the second electrode embedded in the contact hole includes tungsten.
SCHWETLICK teaches a device wherein the portion of the second electrode embedded in the contact hole includes tungsten (310 can be Tungsten, see fig 4, para 74).
MIYATA, NAKAO and SCHWETLICK are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of MIYATA and NAKAO with the material of SCHWETLICK because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of MIYATA and NAKAO with the material of SCHWETLICK in order to reduce the on-state resistance (see SCHWETLICK para 59).
Regarding claim 55, MIYATA and NAKAO disclose the semiconductor device according to Claim 36.
MIYATA and NAKAO fails to explicitly disclose a device, further comprising:
a gate finger portion that is arranged below the first insulating layer and that is electrically connected to the gate electrode of the switching element and
wherein the first insulating layer has a through hole that exposes the gate finger portion,
the first electrode has a portion that is electrically connected to the gate finger portion via the through hole, and
the portion of the first electrode embedded in the through hole includes tungsten.
SCHWETLICK teaches a device, further comprising:
a gate finger portion (fig 4, 165a, para 67) that is arranged below the first insulating layer (165a is below 210, see fig 4, para 71) and that is electrically connected to the gate electrode of the switching element (165a is connected to gate electrode 165b, see fig 4, para 64); and
wherein the first insulating layer has a through hole that exposes the gate finger portion (the through hole in 210 in which 315b is formed, see fig 4B),
the first electrode has a portion that is electrically connected to the gate finger portion via the through hole (first electrode 310 has a portion 315b which connects to 165a, see fig 4B, para 74), and
the portion of the first electrode embedded in the through hole includes tungsten (310 can be Tungsten, see fig 4, para 74).
MIYATA, NAKAO and SCHWETLICK are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of MIYATA and NAKAO with the material of SCHWETLICK because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of MIYATA and NAKAO with the material of SCHWETLICK in order to reduce the on-state resistance (see SCHWETLICK para 59).
Claim(s) 51-53 and 56-58 is/are rejected under 35 U.S.C. 103 as being unpatentable over MIYATA (US 20100187640) in view of NAKAO (US 20200185517) and further in view of NASU (US 20180096991).
Regarding claim 51, MIYATA and NAKAO disclose the semiconductor device according to Claim 21.
MIYATA and NAKAO fails to explicitly disclose a device, further comprising:
metal layers that are formed on upper surfaces of the first terminal electrode and the second terminal electrode, and that are made of metal materials different from metal materials of the first terminal electrode and the second terminal electrode.
NASU teaches a device, further comprising:
metal layers (Ni layer 165, Pd layer 166 and Au layer 167, see fig 23, para 211) that are formed on upper surfaces of the first terminal electrode and the second terminal electrode (these bumps are formed on the source and gate pads, see fig 23, para 211), and that are made of metal materials different from metal materials of the first terminal electrode and the second terminal electrode (155 can be Ti, which is different from the Ni of 165, see fig 23, para 205).
MIYATA, NAKAO and NASU are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of MIYATA and NAKAO with the connection elements of NASU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of MIYATA and NAKAO with the connection elements of NASU in order to suppress an increase in the on-resistance (see NASU para 212).
Regarding claim 52, MIYATA and NAKAO disclose the semiconductor device according to Claim 51.
MIYATA and NAKAO fail to explicitly disclose a device.
wherein each of the metal layers has any one of a single-layer structure composed of a nickel layer, a laminated structure including a nickel layer and a gold layer, a laminated structure including a nickel layer and a palladium layer, and a laminated structure including a nickel layer, a palladium layer and a gold layer.
NASU teaches a device, wherein each of the metal layers has any one of a single-layer structure composed of a nickel layer, a laminated structure including a nickel layer and a gold layer, a laminated structure including a nickel layer and a palladium layer, and a laminated structure including a nickel layer, a palladium layer and a gold layer (Ni layer 165, Pd layer 166 and Au layer 167, see fig 23, para 211).
MIYATA, NAKAO and NASU are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of MIYATA with the connection elements of NASU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of MIYATA and NAKAO with the connection elements of NASU in order to suppress an increase in the on-resistance (see NASU para 212).
Regarding claim 53, MIYATA, NASU and NAKAO disclose the semiconductor device according to Claim 51.
MIYATA further discloses a device, further comprising:
a bonding wire that is connected to the metal layer formed on the first terminal electrode (the pads can be bonded to a bonding wire 48, see fig 9, para 134-135); and
a metal plate (the pads can be bonded to a metal plate, see fig 9, para 134-135) that is connected to the metal layer formed on the second terminal electrode via a bonding material.
Regarding claim 56, MIYATA and NAKAO disclose the semiconductor device according to Claim 36.
MIYATA and NAKAO fail to explicitly disclose a device, further comprising:
metal layers that are formed on upper surfaces of the first terminal electrode and the second terminal electrode, and that are made of metal materials different from metal materials of the first terminal electrode and the second terminal electrode.
NASU teaches a device, further comprising:
metal layers (Ni layer 165, Pd layer 166 and Au layer 167, see fig 23, para 211) that are formed on upper surfaces of the first terminal electrode and the second terminal electrode (these bumps are formed on the source and gate pads, see fig 23, para 211), and that are made of metal materials different from metal materials of the first terminal electrode and the second terminal electrode (155 can be Ti, which is different from the Ni of 165, see fig 23, para 205).
MIYATA, NAKAO and NASU are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of MIYATA and NAKAO with the connection elements of NASU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of MIYATA and NAKAO with the connection elements of NASU in order to suppress an increase in the on-resistance (see NASU para 212).
Regarding claim 57, MIYATA and NAKAO disclose the semiconductor device according to Claim 56.
MIYATA and NAKAO fail to explicitly disclose a device,
wherein each of the metal layers has any one of a single-layer structure composed of a nickel layer, a laminated structure including a nickel layer and a gold layer, a laminated structure including a nickel layer and a palladium layer, and a laminated structure including a nickel layer, a palladium layer and a gold layer.
NASU teaches a device,
wherein each of the metal layers has any one of a single-layer structure composed of a nickel layer, a laminated structure including a nickel layer and a gold layer, a laminated structure including a nickel layer and a palladium layer, and a laminated structure including a nickel layer, a palladium layer and a gold layer (Ni layer 165, Pd layer 166 and Au layer 167, see fig 23, para 211).
MIYATA, NAKAO and NASU are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of MIYATA and NAKAO with the connection elements of NASU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of MIYATA and NAKAO with the connection elements of NASU in order to suppress an increase in the on-resistance (see NASU para 212).
Regarding claim 58, MIYATA, NASU and NAKAO disclose the semiconductor device according to Claim 51.
MIYATA further discloses a device, further comprising:
a bonding wire that is connected to the metal layer formed on the first terminal electrode (the pads can be bonded to a bonding wire 48, see fig 9, para 134-135); and
a metal plate (the pads can be bonded to a metal plate, see fig 9, para 134-135) that is connected to the metal layer formed on the second terminal electrode via a bonding material.
Response to Arguments
Applicant's arguments filed 12/29/2025 have been fully considered but they are not persuasive.
Regarding claims 21 and 36, the applicant argues that MIYATA and NAKAO do not disclose the device of the claims because neither MIYATA nor NAKAO discloses a device wherein “the second insulating layer covers the first electrode, the first terminal electrode has a portion that faces the first electrode across the second insulating layer, and the second terminal electrode has a portion that faces the first electrode across the second insulating layer”. This argument is unpersuasive because MIYATA discloses, in figure 3, a device wherein a part of the first terminal electrode 28 faces the first electrode 18 in the vertical direction with insulator layer 16 therebetween, and wherein a part of the second terminal electrode 27 faces the first electrode 18 in the horizontal direction with the insulator 16 therebetween. For at least this reason, and those given in the rejection above, claims 21 and 36 are not patentable over MIYATA in view of NAKAO.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/LYNNE A GURLEY/Supervisory Patent Examiner, Art Unit 2811