Prosecution Insights
Last updated: October 22, 2026
Application No. 18/883,125

METHODS FOR FORMING A METAL SILICATE LAYER FOR CONTROLLING A THRESHOLD VOLTAGE OF A METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR

Non-Final OA §103
Filed
Sep 12, 2024
Priority
Sep 13, 2023 — provisional 63/582,397
Examiner
RODRIGUEZ, MICHAEL P
Art Unit
Tech Center
Assignee
ASM IP Holding B.V.
OA Round
1 (Non-Final)
73%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allowance Rate
501 granted / 683 resolved
+13.4% vs TC avg
Strong +29% interview lift
Without
With
+29.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
32 currently pending
Career history
715
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
48.0%
+8.0% vs TC avg
§102
18.2%
-21.8% vs TC avg
§112
23.7%
-16.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 683 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statements (IDS) submitted on 12 September 2024 and 29 October 2024 have been considered by the examiner. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 1. Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0122891 to Wang et al. (“Wang”) in view of US 2006/0127578 to Lei et al. (“Lei”). With regard to Claims 1 and 4-7, Wang teaches a method of forming a metal silicate layer for controlling threshold voltage of a metal-oxide-semiconductor field effect transistor comprising forming a metal silicate threshold voltage shifting layer on a substrate featuring a treated dielectric surface (see Abstract; FIGs. 2A-2C, 3; ¶¶ [0002], [0007], [0016]-[0019], [0032]). Wang teaches forming aluminum silicate, titanium silicate, hafnium silicate, and zirconium silicate (see ¶ [0019]). Wang refers to deposition techniques within the context of semiconductor fabrication processes; however the reference does not expressly teach forming layers via precursors in a reaction chamber. Lei is directed to precursor compositions for forming metal silicate layers in semiconductor fabrication processes, and teaches the claimed organosilanol precursors for use in vapor deposition processes (see Abstract; ¶¶ [0012]-[0015], [0028]). Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have deposited metal silicate films using the organosilanol precursors taught by Lei in a vapor deposition reaction chamber in the method of Wang. With regard to Claim 2, Wang teaches silicon oxide dielectric surfaces (see ¶ [0022]). With regard to Claim 3, Wang teaches steps of treating an underlying silicon oxide dielectric surface via contacting with a Zr, Al, Ti, Mg, Hf, Ta, Sr, or Ba metal prior to additional formation of a metal silicate layer (see FIG. 3 steps 124, 126, 128). 2. Claims 1-3 and 8-19 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of US 6,399,208 to Baum et al. (“Baum”). With regard to Claims 1-2 and 8-19, Wang teaches a method of forming a metal silicate layer for controlling threshold voltage of a metal-oxide-semiconductor field effect transistor comprising forming a metal silicate threshold voltage shifting layer on a substrate featuring a treated dielectric surface (see Abstract; FIGs. 2A-2C, 3; ¶¶ [0002], [0007], [0016]-[0019], [0032]). Wang teaches forming aluminum silicate, titanium silicate, hafnium silicate, and zirconium silicate (see ¶ [0019]). Wang teaches silicon oxide dielectric surfaces (see ¶ [0022]). Wang refers to deposition techniques within the context of semiconductor fabrication processes; however the reference does not expressly teach forming layers via a precursor in a reaction chamber. Baum is directed to single source metal siloxide precursors for forming zirconium and/or hafnium silicate films on semiconductor substrates in vapor deposition manufacturing of microelectronic devices, and teaches the claimed single source precursor compositions, including homoleptic and heteroleptic siloxide compositions (see Abstract; Col. 1, Lns. 31-43; Col. 4, Lns. 22-26; Col. 8, Lns. 16-29; Claims 1, 18, 22, 24). Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have deposited metal silicate films using the single source metal siloxide precursors taught by Lei in a vapor deposition reaction chamber in the method of Wang. With regard to Claim 3, Wang teaches steps of treating an underlying silicon oxide dielectric surface via contacting with a Zr, Al, Ti, Mg, Hf, Ta, Sr, or Ba metal prior to additional formation of a metal silicate layer (see FIG. 3 steps 124, 126, 128). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2004/0044163 to Clark et al. teaches organosilanol precursors to form metal silicate layers which read upon Claims 4-7 (see Clark at Abstract; ¶ [0013]). Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michael P Rodriguez whose telephone number is (571)270-3736. The examiner can normally be reached 9:00 - 6:00 Eastern M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael Cleveland can be reached at 571-272-1418. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Michael P. Rodriguez/Primary Examiner, Art Unit 1712
Read full office action

Prosecution Timeline

Sep 12, 2024
Application Filed
Oct 05, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
73%
Grant Probability
99%
With Interview (+29.1%)
2y 8m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 683 resolved cases by this examiner. Grant probability derived from career allowance rate.

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